Lines Matching refs:errata
333 specific physical addresses or enable errata workarounds that may
616 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
625 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
634 bool "ARM errata: Stale prediction on replaced interworking branch"
650 bool "ARM errata: Processor deadlock when a false hazard is created"
666 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
681 bool "ARM errata: DMB operation may be faulty"
697 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
715 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
726 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
738 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
754 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
769 bool "ARM errata: possible faulty MMU translations following an ASID switch"
780 bool "ARM errata: no automatic Store Buffer drain"
791 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
803 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
817 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
828 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
838 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
848 bool "ARM errata: incorrect instructions may be executed from loop buffer"
857 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
866 This workaround for all both errata involves setting bit[12] of the
871 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
881 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
890 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
898 bool "ARM errata: A17: DMB ST might fail to create order between stores"
907 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
915 config option from the A12 erratum due to the way errata are checked
919 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
925 config option from the A12 erratum due to the way errata are checked
948 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"