Lines Matching refs:clks
83 clocks = <&clks IMX5_CLK_CPU_PODF>;
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
138 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
148 clocks = <&clks IMX5_CLK_IPU_GATE>,
149 <&clks IMX5_CLK_IPU_DI0_GATE>,
150 <&clks IMX5_CLK_IPU_DI1_GATE>;
195 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
196 <&clks IMX5_CLK_DUMMY>,
197 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
206 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
207 <&clks IMX5_CLK_DUMMY>,
208 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
218 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
219 <&clks IMX5_CLK_UART3_PER_GATE>;
232 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
233 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
243 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
244 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
257 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
258 <&clks IMX5_CLK_DUMMY>,
259 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
269 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
270 <&clks IMX5_CLK_DUMMY>,
271 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
287 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
297 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
307 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
317 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
327 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
374 clocks = <&clks IMX5_CLK_DUMMY>;
382 clocks = <&clks IMX5_CLK_DUMMY>;
389 clocks = <&clks IMX5_CLK_DUMMY>;
397 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
398 <&clks IMX5_CLK_GPT_HF_GATE>;
411 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
412 <&clks IMX5_CLK_PWM1_HF_GATE>;
421 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
422 <&clks IMX5_CLK_PWM2_HF_GATE>;
431 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
432 <&clks IMX5_CLK_UART1_PER_GATE>;
443 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
444 <&clks IMX5_CLK_UART2_PER_GATE>;
458 clks: ccm@73fd4000{ label
482 clocks = <&clks IMX5_CLK_IIM_GATE>;
494 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
504 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
505 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
514 clocks = <&clks IMX5_CLK_SDMA_GATE>,
515 <&clks IMX5_CLK_AHB>;
527 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
528 <&clks IMX5_CLK_CSPI_IPG_GATE>;
539 clocks = <&clks IMX5_CLK_I2C2_GATE>;
549 clocks = <&clks IMX5_CLK_I2C1_GATE>;
558 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
559 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
571 clocks = <&clks IMX5_CLK_DUMMY>;
586 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
604 clocks = <&clks IMX5_CLK_NFC_GATE>;
612 clocks = <&clks IMX5_CLK_PATA_GATE>;
621 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
622 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
635 clocks = <&clks IMX5_CLK_FEC_GATE>,
636 <&clks IMX5_CLK_FEC_GATE>,
637 <&clks IMX5_CLK_FEC_GATE>;
646 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
647 <&clks IMX5_CLK_VPU_GATE>;
657 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
658 <&clks IMX5_CLK_SAHARA_IPG_GATE>;