Lines Matching refs:clks
68 clocks = <&clks IMX6SLL_CLK_ARM>,
69 <&clks IMX6SLL_CLK_PLL2_PFD2>,
70 <&clks IMX6SLL_CLK_STEP>,
71 <&clks IMX6SLL_CLK_PLL1_SW>,
72 <&clks IMX6SLL_CLK_PLL1_SYS>;
162 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
163 <&clks IMX6SLL_CLK_OSC>,
164 <&clks IMX6SLL_CLK_SPDIF>,
165 <&clks IMX6SLL_CLK_DUMMY>,
166 <&clks IMX6SLL_CLK_DUMMY>,
167 <&clks IMX6SLL_CLK_DUMMY>,
168 <&clks IMX6SLL_CLK_IPG>,
169 <&clks IMX6SLL_CLK_DUMMY>,
170 <&clks IMX6SLL_CLK_DUMMY>,
171 <&clks IMX6SLL_CLK_SPBA>;
186 clocks = <&clks IMX6SLL_CLK_ECSPI1>,
187 <&clks IMX6SLL_CLK_ECSPI1>;
198 clocks = <&clks IMX6SLL_CLK_ECSPI2>,
199 <&clks IMX6SLL_CLK_ECSPI2>;
210 clocks = <&clks IMX6SLL_CLK_ECSPI3>,
211 <&clks IMX6SLL_CLK_ECSPI3>;
222 clocks = <&clks IMX6SLL_CLK_ECSPI4>,
223 <&clks IMX6SLL_CLK_ECSPI4>;
235 clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
236 <&clks IMX6SLL_CLK_UART4_SERIAL>;
248 clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
249 <&clks IMX6SLL_CLK_UART1_SERIAL>;
261 clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
262 <&clks IMX6SLL_CLK_UART2_SERIAL>;
274 clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
275 <&clks IMX6SLL_CLK_SSI1>;
287 clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
288 <&clks IMX6SLL_CLK_SSI2>;
300 clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
301 <&clks IMX6SLL_CLK_SSI3>;
313 clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
314 <&clks IMX6SLL_CLK_UART3_SERIAL>;
324 clocks = <&clks IMX6SLL_CLK_PWM1>,
325 <&clks IMX6SLL_CLK_PWM1>;
334 clocks = <&clks IMX6SLL_CLK_PWM2>,
335 <&clks IMX6SLL_CLK_PWM2>;
344 clocks = <&clks IMX6SLL_CLK_PWM3>,
345 <&clks IMX6SLL_CLK_PWM3>;
354 clocks = <&clks IMX6SLL_CLK_PWM4>,
355 <&clks IMX6SLL_CLK_PWM4>;
364 clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
365 <&clks IMX6SLL_CLK_GPT_SERIAL>;
374 clocks = <&clks IMX6SLL_CLK_GPIO1>;
387 clocks = <&clks IMX6SLL_CLK_GPIO2>;
400 clocks = <&clks IMX6SLL_CLK_GPIO3>;
415 clocks = <&clks IMX6SLL_CLK_GPIO4>;
436 clocks = <&clks IMX6SLL_CLK_GPIO5>;
459 clocks = <&clks IMX6SLL_CLK_GPIO6>;
470 clocks = <&clks IMX6SLL_CLK_KPP>;
478 clocks = <&clks IMX6SLL_CLK_WDOG1>;
485 clocks = <&clks IMX6SLL_CLK_WDOG2>;
489 clks: clock-controller@20c4000 { label
498 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
499 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
535 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
544 clocks = <&clks IMX6SLL_CLK_USBPHY1>;
554 clocks = <&clks IMX6SLL_CLK_USBPHY2>;
621 clocks = <&clks IMX6SLL_CLK_DUMMY>,
622 <&clks IMX6SLL_CLK_CSI>,
623 <&clks IMX6SLL_CLK_DUMMY>;
632 clocks = <&clks IMX6SLL_CLK_IPG>,
633 <&clks IMX6SLL_CLK_SDMA>;
645 clocks = <&clks IMX6SLL_CLK_PXP>;
653 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
654 <&clks IMX6SLL_CLK_LCDIF_APB>,
655 <&clks IMX6SLL_CLK_DUMMY>;
666 clocks = <&clks IMX6SLL_CLK_DCP>;
683 clocks = <&clks IMX6SLL_CLK_USBOH3>;
698 clocks = <&clks IMX6SLL_CLK_USBOH3>;
718 clocks = <&clks IMX6SLL_CLK_USDHC1>,
719 <&clks IMX6SLL_CLK_USDHC1>,
720 <&clks IMX6SLL_CLK_USDHC1>;
732 clocks = <&clks IMX6SLL_CLK_USDHC2>,
733 <&clks IMX6SLL_CLK_USDHC2>,
734 <&clks IMX6SLL_CLK_USDHC2>;
746 clocks = <&clks IMX6SLL_CLK_USDHC3>,
747 <&clks IMX6SLL_CLK_USDHC3>,
748 <&clks IMX6SLL_CLK_USDHC3>;
762 clocks = <&clks IMX6SLL_CLK_I2C1>;
772 clocks = <&clks IMX6SLL_CLK_I2C2>;
782 clocks = <&clks IMX6SLL_CLK_I2C3>;
789 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
796 clocks = <&clks IMX6SLL_CLK_DUMMY>;
804 clocks = <&clks IMX6SLL_CLK_OCOTP>;
832 clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
833 <&clks IMX6SLL_CLK_UART5_SERIAL>;