Lines Matching refs:topckgen
126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
342 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
343 <&topckgen CLK_TOP_SPI0_SEL>,
389 <&topckgen CLK_TOP_FLASH_SEL>;
402 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
403 <&topckgen CLK_TOP_SPI1_SEL>,
415 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
416 <&topckgen CLK_TOP_SPI2_SEL>,
435 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
436 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
437 <&topckgen CLK_TOP_AUD_48K_TIMING>,
438 <&topckgen CLK_TOP_AUD_44K_TIMING>,
439 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
440 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
441 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
442 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
443 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
444 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
445 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
446 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
447 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
448 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
449 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
450 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
504 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
505 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
506 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
507 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
508 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
509 <&topckgen CLK_TOP_AUD2PLL_90M>;
613 <&topckgen CLK_TOP_ETHIF_SEL>;
631 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
653 <&topckgen CLK_TOP_ETHIF_SEL>;
671 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
713 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
733 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,