Lines Matching refs:topckgen
226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
277 clocks = <&topckgen CLK_TOP_MM_SEL>,
278 <&topckgen CLK_TOP_MFG_SEL>,
279 <&topckgen CLK_TOP_ETHIF_SEL>;
423 clocks = <&topckgen CLK_TOP_PWM_SEL>,
487 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
488 <&topckgen CLK_TOP_SPI0_SEL>,
552 <&topckgen CLK_TOP_FLASH_SEL>;
566 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
567 <&topckgen CLK_TOP_SPI1_SEL>,
580 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
581 <&topckgen CLK_TOP_SPI2_SEL>,
614 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
636 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
637 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
638 <&topckgen CLK_TOP_AUD_48K_TIMING>,
639 <&topckgen CLK_TOP_AUD_44K_TIMING>,
640 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
641 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
642 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
643 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
644 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
645 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
646 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
647 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
648 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
649 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
650 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
651 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
705 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
706 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
707 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
708 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
709 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
710 <&topckgen CLK_TOP_AUD2PLL_90M>;
721 <&topckgen CLK_TOP_MSDC30_0_SEL>;
732 <&topckgen CLK_TOP_MSDC30_1_SEL>;
769 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
866 <&topckgen CLK_TOP_ETHIF_SEL>;
884 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
907 <&topckgen CLK_TOP_ETHIF_SEL>;
925 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
967 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,