Lines Matching refs:psc
76 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_clk_is_enabled() local
77 u32 val = readl(psc->reg); in ep93xx_clk_is_enabled()
79 return (val & BIT(psc->bit_idx)) ? 1 : 0; in ep93xx_clk_is_enabled()
84 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_clk_enable() local
88 if (psc->lock) in ep93xx_clk_enable()
89 spin_lock_irqsave(psc->lock, flags); in ep93xx_clk_enable()
91 val = __raw_readl(psc->reg); in ep93xx_clk_enable()
92 val |= BIT(psc->bit_idx); in ep93xx_clk_enable()
94 ep93xx_syscon_swlocked_write(val, psc->reg); in ep93xx_clk_enable()
96 if (psc->lock) in ep93xx_clk_enable()
97 spin_unlock_irqrestore(psc->lock, flags); in ep93xx_clk_enable()
104 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_clk_disable() local
108 if (psc->lock) in ep93xx_clk_disable()
109 spin_lock_irqsave(psc->lock, flags); in ep93xx_clk_disable()
111 val = __raw_readl(psc->reg); in ep93xx_clk_disable()
112 val &= ~BIT(psc->bit_idx); in ep93xx_clk_disable()
114 ep93xx_syscon_swlocked_write(val, psc->reg); in ep93xx_clk_disable()
116 if (psc->lock) in ep93xx_clk_disable()
117 spin_unlock_irqrestore(psc->lock, flags); in ep93xx_clk_disable()
132 struct clk_psc *psc; in ep93xx_clk_register_gate() local
135 psc = kzalloc(sizeof(*psc), GFP_KERNEL); in ep93xx_clk_register_gate()
136 if (!psc) in ep93xx_clk_register_gate()
145 psc->reg = reg; in ep93xx_clk_register_gate()
146 psc->bit_idx = bit_idx; in ep93xx_clk_register_gate()
147 psc->hw.init = &init; in ep93xx_clk_register_gate()
148 psc->lock = &clk_lock; in ep93xx_clk_register_gate()
150 clk = clk_register(NULL, &psc->hw); in ep93xx_clk_register_gate()
152 kfree(psc); in ep93xx_clk_register_gate()
156 return &psc->hw; in ep93xx_clk_register_gate()
161 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_mux_get_parent() local
162 u32 val = __raw_readl(psc->reg); in ep93xx_mux_get_parent()
175 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_mux_set_parent_lock() local
182 if (psc->lock) in ep93xx_mux_set_parent_lock()
183 spin_lock_irqsave(psc->lock, flags); in ep93xx_mux_set_parent_lock()
185 val = __raw_readl(psc->reg); in ep93xx_mux_set_parent_lock()
194 ep93xx_syscon_swlocked_write(val, psc->reg); in ep93xx_mux_set_parent_lock()
196 if (psc->lock) in ep93xx_mux_set_parent_lock()
197 spin_unlock_irqrestore(psc->lock, flags); in ep93xx_mux_set_parent_lock()
262 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_ddiv_recalc_rate() local
264 u32 val = __raw_readl(psc->reg); in ep93xx_ddiv_recalc_rate()
277 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_ddiv_set_rate() local
301 val = __raw_readl(psc->reg); in ep93xx_ddiv_set_rate()
308 ep93xx_syscon_swlocked_write(val, psc->reg); in ep93xx_ddiv_set_rate()
329 struct clk_psc *psc; in clk_hw_register_ddiv() local
332 psc = kzalloc(sizeof(*psc), GFP_KERNEL); in clk_hw_register_ddiv()
333 if (!psc) in clk_hw_register_ddiv()
342 psc->reg = reg; in clk_hw_register_ddiv()
343 psc->bit_idx = bit_idx; in clk_hw_register_ddiv()
344 psc->lock = &clk_lock; in clk_hw_register_ddiv()
345 psc->hw.init = &init; in clk_hw_register_ddiv()
347 clk = clk_register(NULL, &psc->hw); in clk_hw_register_ddiv()
349 kfree(psc); in clk_hw_register_ddiv()
352 return &psc->hw; in clk_hw_register_ddiv()
358 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_div_recalc_rate() local
359 u32 val = __raw_readl(psc->reg); in ep93xx_div_recalc_rate()
360 u8 index = (val & psc->mask) >> psc->shift; in ep93xx_div_recalc_rate()
362 if (index > psc->num_div) in ep93xx_div_recalc_rate()
365 return DIV_ROUND_UP_ULL(parent_rate, psc->div[index]); in ep93xx_div_recalc_rate()
371 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_div_round_rate() local
375 maxdiv = psc->div[psc->num_div - 1]; in ep93xx_div_round_rate()
377 for (i = 0; i < psc->num_div; i++) { in ep93xx_div_round_rate()
378 if ((rate * psc->div[i]) == *parent_rate) in ep93xx_div_round_rate()
379 return DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); in ep93xx_div_round_rate()
381 now = DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]); in ep93xx_div_round_rate()
396 struct clk_psc *psc = to_clk_psc(hw); in ep93xx_div_set_rate() local
397 u32 val = __raw_readl(psc->reg) & ~psc->mask; in ep93xx_div_set_rate()
400 for (i = 0; i < psc->num_div; i++) in ep93xx_div_set_rate()
401 if (rate == parent_rate / psc->div[i]) { in ep93xx_div_set_rate()
402 val |= i << psc->shift; in ep93xx_div_set_rate()
406 if (i == psc->num_div) in ep93xx_div_set_rate()
409 ep93xx_syscon_swlocked_write(val, psc->reg); in ep93xx_div_set_rate()
433 struct clk_psc *psc; in clk_hw_register_div() local
436 psc = kzalloc(sizeof(*psc), GFP_KERNEL); in clk_hw_register_div()
437 if (!psc) in clk_hw_register_div()
446 psc->reg = reg; in clk_hw_register_div()
447 psc->bit_idx = enable_bit; in clk_hw_register_div()
448 psc->mask = GENMASK(shift + width - 1, shift); in clk_hw_register_div()
449 psc->shift = shift; in clk_hw_register_div()
450 psc->div = clk_divisors; in clk_hw_register_div()
451 psc->num_div = num_div; in clk_hw_register_div()
452 psc->lock = &clk_lock; in clk_hw_register_div()
453 psc->hw.init = &init; in clk_hw_register_div()
455 clk = clk_register(NULL, &psc->hw); in clk_hw_register_div()
457 kfree(psc); in clk_hw_register_div()
460 return &psc->hw; in clk_hw_register_div()