Lines Matching refs:ldr
37 ldr r1, =CPU_MASK
39 ldr r1, =CPU_CORTEX_A9
51 ldr r1, =CPU_MASK
53 ldr r1, =CPU_CORTEX_A9
58 ldr r1, [r0]
59 ldr r1, [r0, r1]
61 ldr r2, [r0]
62 ldr r2, [r0, r2]
68 ldr r2, [r0]
72 ldr r1, [r0, #L2X0_R_PHY_BASE]
77 ldr r2, [r1, #L2X0_CTRL]
81 ldr r1, [r0, #L2X0_R_TAG_LATENCY]
82 ldr r2, [r0, #L2X0_R_DATA_LATENCY]
83 ldr r3, [r0, #L2X0_R_PREFETCH_CTRL]
89 ldr r2, [r0]
92 ldr r1, [r0, #L2X0_R_PWR_CTRL]
93 ldr r2, [r0, #L2X0_R_AUX_CTRL]