Lines Matching refs:ldr
78 ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
84 ldr r6, [r11, #L2X0_CACHE_SYNC]
99 ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
100 ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
103 ldr r8, [r7], #0x4
104 ldr r9, [r7], #0x4
117 ldr r7, =MX6Q_MMDC_MPDGCTRL0
118 ldr r6, [r11, r7]
122 ldr r6, [r11, r7]
127 ldr r6, [r11, r7]
131 ldr r6, [r11, r7]
136 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
140 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
145 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
152 ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
153 ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
154 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
155 ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
161 ldr r6, =imx6_suspend
162 ldr r7, =resume
172 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
173 ldr r6, [r11, #0x0]
174 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
175 ldr r6, [r11, #0x0]
176 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
177 ldr r6, [r11, #0x0]
180 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
188 ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
193 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
198 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
203 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
207 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
208 ldr r6, =0x0
209 ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
210 ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
216 ldr r9, [r8], #0x8
223 ldr r6, =0x1000
224 ldr r9, [r8], #0x8
226 ldr r9, [r8], #0x8
228 ldr r6, =0x80000
229 ldr r9, [r8]
240 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
241 ldr r6, [r11, #MX6Q_GPC_IMR1]
242 ldr r7, [r11, #MX6Q_GPC_IMR2]
243 ldr r8, [r11, #MX6Q_GPC_IMR3]
244 ldr r9, [r11, #MX6Q_GPC_IMR4]
246 ldr r10, =0xffffffff
258 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
259 ldr r10, [r11, #MX6Q_CCM_CCR]
265 ldr r10, [r11, #MX6Q_CCM_CCR]
270 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
286 ldr r6, =2000
320 ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
322 ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
327 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]