Lines Matching refs:MV78XX0_REGS_VIRT_BASE
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000) macro
67 #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
74 #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
92 #define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
93 #define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
94 #define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
95 #define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
104 #define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
105 #define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
106 #define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
107 #define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)