Lines Matching refs:ldr
71 ldr r9, [r0, #OMAP_TYPE_OFFSET]
77 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
105 ldr r9, [r8, #OMAP_TYPE_OFFSET]
114 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
159 ldr r0, =0xffff
162 ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
163 ldr r1, =0xffff
177 ldr r0, [r2, #L2X0_CACHE_SYNC]
208 ldr r9, [r8, #OMAP_TYPE_OFFSET]
214 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
249 ldr r8, =OMAP44XX_SAR_RAM_BASE
250 ldr r9, [r8, #OMAP_TYPE_OFFSET]
259 ldr r3, [r1]
285 ldr r2, =OMAP44XX_L2CACHE_BASE
286 ldr r0, [r2, #L2X0_CTRL]
290 ldr r3, =OMAP44XX_SAR_RAM_BASE
291 ldr r1, [r3, #OMAP_TYPE_OFFSET]
294 ldr r0, =OMAP4_PPA_L2_POR_INDEX
295 ldr r1, =OMAP44XX_SAR_RAM_BASE
296 ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
298 ldr r3, [r1]
308 ldr r1, =OMAP44XX_SAR_RAM_BASE
309 ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
310 ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
313 ldr r1, =OMAP44XX_SAR_RAM_BASE
314 ldr r0, [r1, #L2X0_AUXCTRL_OFFSET]
315 ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
318 ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache