Lines Matching refs:r0
63 cmp r0, #0x0
71 ldr r9, [r0, #OMAP_TYPE_OFFSET]
74 mov r0, #SCU_PM_NORMAL
88 mrc p15, 0, r0, c1, c0, 0
89 bic r0, r0, #(1 << 2) @ Disable the C bit
90 mcr p15, 0, r0, c1, c0, 0
104 mov r8, r0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
109 ands r0, r0, #0x0f
110 ldreq r0, [r8, #SCU_OFFSET0]
111 ldrne r0, [r8, #SCU_OFFSET1]
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
120 ands r0, r0, #0x0f
126 mrc p15, 0, r0, c1, c1, 2 @ Read NSACR data
127 tst r0, #(1 << 18)
128 mrcne p15, 0, r0, c1, c0, 1
129 bicne r0, r0, #(1 << 6) @ Disable SMP bit
130 mcrne p15, 0, r0, c1, c0, 1
145 mov r8, r0
148 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
149 ldrne r0, [r8, #L2X0_SAVE_OFFSET1] @ memory.
150 cmp r0, #3
153 mov r0, #0x03
158 mov r2, r0
159 ldr r0, =0xffff
160 str r0, [r2, #L2X0_CLEAN_INV_WAY]
162 ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
164 ands r0, r0, r1
167 mov r0, #0x00
173 mov r2, r0
174 mov r0, #0x0
175 str r0, [r2, #L2X0_CACHE_SYNC]
177 ldr r0, [r2, #L2X0_CACHE_SYNC]
178 ands r0, r0, #0x1
189 mrc p15, 0, r0, c1, c0, 0
190 tst r0, #(1 << 2) @ Check C bit enabled?
191 orreq r0, r0, #(1 << 2) @ Enable the C bit
192 mcreq p15, 0, r0, c1, c0, 0
201 mrc p15, 0, r0, c1, c0, 1
202 tst r0, #(1 << 6) @ Check SMP bit enabled?
203 orreq r0, r0, #(1 << 6)
204 mcreq p15, 0, r0, c1, c0, 1
207 mov r8, r0
211 mov r0, #SCU_PM_NORMAL
253 mrc p15, 0, r0, c0, c0, 5
254 ands r0, r0, #0x0f
257 mov r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX
266 cmp r0, #0x0 @ API returns 0 on success.
270 mrc p15, 0, r0, c1, c0, 1
271 tst r0, #(1 << 6) @ Check SMP bit enabled?
272 orreq r0, r0, #(1 << 6)
273 mcreq p15, 0, r0, c1, c0, 1
286 ldr r0, [r2, #L2X0_CTRL]
287 and r0, #0x0f
288 cmp r0, #1
294 ldr r0, =OMAP4_PPA_L2_POR_INDEX
309 ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
314 ldr r0, [r1, #L2X0_AUXCTRL_OFFSET]
317 mov r0, #0x1