Lines Matching refs:Nb
57 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ argument
58 (0x20000000 + (Nb)*PCMCIASp)
59 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ argument
60 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ argument
61 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
62 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ argument
63 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
267 #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */ argument
268 #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */ argument
269 #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */ argument
270 #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */ argument
271 #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */ argument
272 #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */ argument
273 #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */ argument
274 #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */ argument
843 #define OSSR_M(Nb) /* Match detected [0..3] */ \ argument
844 (0x00000001 << (Nb))
853 #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \ argument
854 (0x00000001 << (Nb))
902 #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */ argument
1117 #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \ argument
1118 (0x00000001 << (Nb))
1148 #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \ argument
1149 GPIO_GPIO ((Nb) - 6)
1217 #define IC_GPIO(Nb) /* GPIO [0..10] */ \ argument
1218 (0x00000001 << (Nb))
1239 #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \ argument
1240 (0x00100000 << (Nb))
1247 #define IC_OST(Nb) /* OS Timer match [0..3] */ \ argument
1248 (0x04000000 << (Nb))
1289 #define PPC_LDD(Nb) /* LCD Data [0..7] */ \ argument
1290 (0x00000001 << (Nb))
1374 #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \ argument
1375 (0x00000001 << (Nb))
1447 #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \ argument
1448 Fld (16, ((Nb) Modulo 2)*16)
1515 #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \ argument
1516 Fld (15, (Nb)*16)