Lines Matching refs:__REG
111 #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
112 #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
113 #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
114 #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
115 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
116 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
117 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
118 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
119 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
120 #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */
121 #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */
267 #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */
268 #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */
269 #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */
270 #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */
271 #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */
272 #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */
273 #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */
274 #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */
429 #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */
430 #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */
431 #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */
432 #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */
433 #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */
434 #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */
435 #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */
436 #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */
543 #define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */
544 #define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */
545 #define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */
546 #define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */
547 #define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */
548 #define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */
630 #define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */
631 #define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */
632 #define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */
633 #define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */
634 #define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */
635 #define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */
753 #define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */
754 #define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */
755 #define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */
756 #define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */
884 #define PMCR __REG(0x90020000) /* PM Control Reg. */
885 #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */
886 #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */
887 #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */
888 #define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */
889 #define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */
890 #define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */
891 #define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */
1025 #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */
1026 #define RCSR __REG(0x90030004) /* RC Status Reg. */
1043 #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */
1105 #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */
1106 #define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */
1107 #define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */
1108 #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */
1109 #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */
1110 #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */
1111 #define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */
1112 #define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */
1210 #define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */
1211 #define ICMR __REG(0x90050004) /* IC Mask Reg. */
1212 #define ICLR __REG(0x90050008) /* IC Level Reg. */
1213 #define ICCR __REG(0x9005000C) /* IC Control Reg. */
1214 #define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */
1215 #define ICPR __REG(0x90050020) /* IC Pending Reg. */
1283 #define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */
1284 #define PPSR __REG(0x90060004) /* PPC Pin State Reg. */
1285 #define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */
1286 #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */
1287 #define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */
1368 #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */
1369 #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */
1370 #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */
1371 #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */
1443 #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */
1444 #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */
1445 #define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */
1513 #define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */
1541 #define MDREFR __REG(0xA000001C)