Lines Matching refs:r9
55 ldr r9, [sp], #4
64 str r9, [sp, #-4]!
68 and r9, r8, r7, lsl #1
69 add r6, r6, r9, lsr #1
70 and r9, r8, r7, lsl #2
71 add r6, r6, r9, lsr #2
72 and r9, r8, r7, lsl #3
73 add r6, r6, r9, lsr #3
77 and r9, r8, #15 << 16 @ Extract 'n' from instruction
78 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
82 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
83 ldr r9, [sp], #4
90 str r9, [sp, #-4]!
91 and r9, r8, #0x00f @ get Rm / low nibble of immediate value
94 orrne r6, r9, r6, lsr #4 @ combine nibbles } else
95 ldreq r6, [r2, r9, lsl #2] @ { load Rm value }
97 and r9, r8, #15 << 16 @ Extract 'n' from instruction
98 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
102 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
103 ldr r9, [sp], #4
112 str r9, [sp, #-4]!
113 and r9, r8, #15 << 16 @ Extract 'n' from instruction
114 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
118 str r7, [r2, r9, lsr #14] @ Put register 'Rn'
119 ldr r9, [sp], #4
128 str r9, [sp, #-4]!
129 mov r9, r8, lsr #7 @ get shift count
130 ands r9, r9, #31
136 mov r6, r6, lsl r9 @ 0: LSL #!0
144 mov r6, r6, lsr r9 @ 4: LSR #!0
152 mov r6, r6, asr r9 @ 8: ASR #!0
160 mov r6, r6, ror r9 @ C: ROR #!0
204 str r9, [sp, #-4]!
206 and r9, r8, #0xaa
207 add r6, r6, r9, lsr #1
208 and r9, r6, #0xcc
210 add r6, r6, r9, lsr #2
219 ldr r9, [sp], #4
223 str r9, [sp, #-4]!
225 and r9, r8, #0xaa
226 add r6, r6, r9, lsr #1
227 and r9, r6, #0xcc
229 add r6, r6, r9, lsr #2
231 and r9, r8, #7 << 8
232 ldr r7, [r2, r9, lsr #6]
235 str r7, [r2, r9, lsr #6]
236 ldr r9, [sp], #4