Lines Matching refs:r0
81 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
82 bic r0, r0, #0x1000 @ ...i............
83 bic r0, r0, #0x000e @ ............wca.
84 mcr p15, 0, r0, c1, c0, 0 @ disable caches
118 ret r0
127 mov r0, #0
129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
142 mov r0, #0
143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
191 sub r3, r1, r0 @ calculate total size
196 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
197 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
198 add r0, r0, #CACHE_DLINESIZE
199 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
201 add r0, r0, #CACHE_DLINESIZE
203 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
205 add r0, r0, #CACHE_DLINESIZE
206 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
207 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
208 add r0, r0, #CACHE_DLINESIZE
210 cmp r0, r1
240 bic r0, r0, #CACHE_DLINESIZE - 1
241 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
242 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
243 add r0, r0, #CACHE_DLINESIZE
244 cmp r0, r1
246 mcr p15, 0, r0, c7, c10, 4 @ drain WB
247 mov r0, #0
260 add r1, r0, r1
261 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
262 add r0, r0, #CACHE_DLINESIZE
263 cmp r0, r1
265 mov r0, #0
266 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
267 mcr p15, 0, r0, c7, c10, 4 @ drain WB
285 tst r0, #CACHE_DLINESIZE - 1
286 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
290 bic r0, r0, #CACHE_DLINESIZE - 1
291 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
292 add r0, r0, #CACHE_DLINESIZE
293 cmp r0, r1
295 mcr p15, 0, r0, c7, c10, 4 @ drain WB
310 bic r0, r0, #CACHE_DLINESIZE - 1
311 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
312 add r0, r0, #CACHE_DLINESIZE
313 cmp r0, r1
316 mcr p15, 0, r0, c7, c10, 4 @ drain WB
328 bic r0, r0, #CACHE_DLINESIZE - 1
331 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
333 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
335 add r0, r0, #CACHE_DLINESIZE
336 cmp r0, r1
338 mcr p15, 0, r0, c7, c10, 4 @ drain WB
348 add r1, r1, r0
373 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
374 add r0, r0, #CACHE_DLINESIZE
378 mcr p15, 0, r0, c7, c10, 4 @ drain WB
405 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
419 mov r0, r0
421 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
423 mcr p15, 0, r0, c7, c10, 4 @ drain WB
429 mov r0, #0
432 orr r0,r0,#1 << 1 @ transparent mode on
433 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
435 mov r0, #0
436 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
437 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
439 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
443 mov r0, #4 @ disable write-back on caches explicitly
444 mcr p15, 7, r0, c15, c0, 0
449 mrc p15, 0, r0, c1, c0 @ get control register v4
450 bic r0, r0, r5
451 orr r0, r0, r6
453 orr r0, r0, #0x4000 @ .1.. .... .... ....