Lines Matching refs:r0
50 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
51 bic r0, r0, #0x1000 @ ...i............
52 bic r0, r0, #0x000e @ ............wca.
53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
78 ret r0
89 mov r0, #0
91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
108 mov r0, #0
109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
154 sub r3, r1, r0 @ calculate total size
159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
161 add r0, r0, #CACHE_DLINESIZE
162 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
164 add r0, r0, #CACHE_DLINESIZE
166 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
167 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
168 add r0, r0, #CACHE_DLINESIZE
169 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
171 add r0, r0, #CACHE_DLINESIZE
173 cmp r0, r1
203 bic r0, r0, #CACHE_DLINESIZE - 1
204 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
205 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
206 add r0, r0, #CACHE_DLINESIZE
207 cmp r0, r1
209 mcr p15, 0, r0, c7, c10, 4 @ drain WB
210 mov r0, #0
223 add r1, r0, r1
224 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
225 add r0, r0, #CACHE_DLINESIZE
226 cmp r0, r1
228 mov r0, #0
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
230 mcr p15, 0, r0, c7, c10, 4 @ drain WB
248 tst r0, #CACHE_DLINESIZE - 1
249 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
253 bic r0, r0, #CACHE_DLINESIZE - 1
254 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
255 add r0, r0, #CACHE_DLINESIZE
256 cmp r0, r1
258 mcr p15, 0, r0, c7, c10, 4 @ drain WB
273 bic r0, r0, #CACHE_DLINESIZE - 1
274 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
275 add r0, r0, #CACHE_DLINESIZE
276 cmp r0, r1
279 mcr p15, 0, r0, c7, c10, 4 @ drain WB
291 bic r0, r0, #CACHE_DLINESIZE - 1
294 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
296 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
298 add r0, r0, #CACHE_DLINESIZE
299 cmp r0, r1
301 mcr p15, 0, r0, c7, c10, 4 @ drain WB
311 add r1, r1, r0
336 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
337 add r0, r0, #CACHE_DLINESIZE
341 mcr p15, 0, r0, c7, c10, 4 @ drain WB
366 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
380 mov r0, r0
382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
384 mcr p15, 0, r0, c7, c10, 4 @ drain WB
397 stmia r0, {r4 - r6}
405 ldmia r0, {r4 - r6}
409 mov r0, r6 @ control register
416 mov r0, #0
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
418 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
420 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
425 mov r0, #4 @ disable write-back on caches explicitly
426 mcr p15, 7, r0, c15, c0, 0
431 mrc p15, 0, r0, c1, c0 @ get control register v4
432 bic r0, r0, r5
433 orr r0, r0, r6
435 orr r0, r0, #0x4000 @ .1.. .... .... ....