Lines Matching refs:topckgen
90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
284 clocks = <&topckgen CLK_TOP_MM_SEL>,
285 <&topckgen CLK_TOP_MFG_SEL>,
286 <&topckgen CLK_TOP_VENC_SEL>,
287 <&topckgen CLK_TOP_JPGDEC_SEL>,
288 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
289 <&topckgen CLK_TOP_VDEC_SEL>;
320 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
321 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
481 clocks = <&topckgen CLK_TOP_PWM_SEL>,
555 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
556 <&topckgen CLK_TOP_SPI_SEL>,
566 clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>;
578 clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>;
634 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
635 <&topckgen CLK_TOP_SPI_SEL>,
647 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
648 <&topckgen CLK_TOP_SPI_SEL>,
660 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
661 <&topckgen CLK_TOP_SPI_SEL>,
673 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
674 <&topckgen CLK_TOP_SPI_SEL>,
742 <&topckgen CLK_TOP_ETHER_125M_SEL>,
743 <&topckgen CLK_TOP_ETHER_50M_SEL>,
744 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
745 assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
746 <&topckgen CLK_TOP_ETHER_50M_SEL>,
747 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
748 assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
749 <&topckgen CLK_TOP_APLL1_D3>,
750 <&topckgen CLK_TOP_ETHERPLL_50M>;
779 <&topckgen CLK_TOP_AXI_SEL>,
790 <&topckgen CLK_TOP_AXI_SEL>,
805 clocks = <&topckgen CLK_TOP_USB30_SEL>;
820 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
869 clocks = <&topckgen CLK_TOP_USB30_SEL>;
884 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
933 clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
965 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,