Lines Matching refs:topckgen
250 clocks = <&topckgen CLK_TOP_HIF_SEL>;
259 <&topckgen CLK_TOP_AXI_SEL>;
292 topckgen: topckgen@10210000 { label
293 compatible = "mediatek,mt7622-topckgen",
332 clocks = <&topckgen CLK_TOP_RTC>;
396 clocks = <&topckgen CLK_TOP_UART_SEL>,
407 clocks = <&topckgen CLK_TOP_UART_SEL>,
418 clocks = <&topckgen CLK_TOP_UART_SEL>,
429 clocks = <&topckgen CLK_TOP_UART_SEL>,
440 clocks = <&topckgen CLK_TOP_PWM_SEL>,
499 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
500 <&topckgen CLK_TOP_SPI0_SEL>,
581 <&topckgen CLK_TOP_FLASH_SEL>;
592 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
593 <&topckgen CLK_TOP_SPI1_SEL>,
606 clocks = <&topckgen CLK_TOP_UART_SEL>,
624 <&topckgen CLK_TOP_AUD1_SEL>,
625 <&topckgen CLK_TOP_AUD2_SEL>,
626 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
627 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
628 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
629 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
630 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
631 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
632 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
633 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
634 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
635 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
636 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
637 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
638 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
639 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
691 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
692 <&topckgen CLK_TOP_A2SYS_HP_SEL>,
693 <&topckgen CLK_TOP_A1SYS_HP_DIV>,
694 <&topckgen CLK_TOP_A2SYS_HP_DIV>;
695 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
696 <&topckgen CLK_TOP_AUD2PLL>;
706 <&topckgen CLK_TOP_MSDC50_0_SEL>;
718 <&topckgen CLK_TOP_AXI_SEL>;
917 clocks = <&topckgen CLK_TOP_ETH_500M>;
975 clocks = <&topckgen CLK_TOP_ETH_SEL>,
984 <&topckgen CLK_TOP_SGMIIPLL>,