Lines Matching refs:topckgen
164 topckgen: topckgen@1001b000 { label
165 compatible = "mediatek,mt7986-topckgen", "syscon";
238 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
251 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
253 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
254 <&topckgen CLK_TOP_UART_SEL>;
267 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
280 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
304 clocks = <&topckgen CLK_TOP_MPLL_D2>,
305 <&topckgen CLK_TOP_SPI_SEL>,
318 clocks = <&topckgen CLK_TOP_MPLL_D2>,
319 <&topckgen CLK_TOP_SPIM_MST_SEL>,
337 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
354 clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
425 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
426 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
433 clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
440 clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
441 <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
517 <&topckgen CLK_TOP_NETSYS_SEL>,
518 <&topckgen CLK_TOP_NETSYS_500M_SEL>;
525 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
526 <&topckgen CLK_TOP_SGM_325M_SEL>;
543 clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
544 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;