Lines Matching refs:mmsys
987 mmsys: syscon@14000000 { label
988 compatible = "mediatek,mt8173-mmsys", "syscon";
1004 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1005 <&mmsys CLK_MM_MUTEX_32K>;
1014 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
1015 <&mmsys CLK_MM_MUTEX_32K>;
1023 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1030 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1037 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
1044 clocks = <&mmsys CLK_MM_MDP_WDMA>;
1052 clocks = <&mmsys CLK_MM_MDP_WROT0>;
1060 clocks = <&mmsys CLK_MM_MDP_WROT1>;
1070 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1080 clocks = <&mmsys CLK_MM_DISP_OVL1>;
1090 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1100 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1110 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1120 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1130 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1140 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1149 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1158 clocks = <&mmsys CLK_MM_DISP_AAL>;
1167 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1175 clocks = <&mmsys CLK_MM_DISP_MERGE>;
1182 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1189 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1197 clocks = <&mmsys CLK_MM_DISP_UFOE>;
1206 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1207 <&mmsys CLK_MM_DSI0_DIGITAL>,
1210 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
1221 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1222 <&mmsys CLK_MM_DSI1_DIGITAL>,
1235 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1236 <&mmsys CLK_MM_DPI_ENGINE>,
1253 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1254 <&mmsys CLK_MM_DISP_PWM0MM>;
1264 clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1265 <&mmsys CLK_MM_DISP_PWM1MM>;
1275 clocks = <&mmsys CLK_MM_MUTEX_32K>;
1286 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1287 <&mmsys CLK_MM_SMI_LARB0>;
1295 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1296 <&mmsys CLK_MM_SMI_COMMON>;
1303 clocks = <&mmsys CLK_MM_DISP_OD>;
1311 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1312 <&mmsys CLK_MM_HDMI_PLLCK>,
1313 <&mmsys CLK_MM_HDMI_AUDIO>,
1314 <&mmsys CLK_MM_HDMI_SPDIF>;
1320 mediatek,syscon-hdmi = <&mmsys 0x900>;
1344 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1345 <&mmsys CLK_MM_SMI_LARB4>;