Lines Matching refs:topckgen
349 topckgen: clock-controller@10000000 { label
350 compatible = "mediatek,mt8173-topckgen";
459 clocks = <&topckgen CLK_TOP_MM_SEL>;
465 clocks = <&topckgen CLK_TOP_MM_SEL>,
466 <&topckgen CLK_TOP_VENC_SEL>;
472 clocks = <&topckgen CLK_TOP_MM_SEL>;
478 clocks = <&topckgen CLK_TOP_MM_SEL>;
485 clocks = <&topckgen CLK_TOP_MM_SEL>,
486 <&topckgen CLK_TOP_VENC_LT_SEL>;
534 <&topckgen CLK_TOP_RTC_SEL>;
562 clocks = <&topckgen CLK_TOP_SCP_SEL>;
761 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
762 <&topckgen CLK_TOP_SPI_SEL>,
785 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
788 <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
858 <&topckgen CLK_TOP_AUDIO_SEL>,
859 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
860 <&topckgen CLK_TOP_APLL1_DIV0>,
861 <&topckgen CLK_TOP_APLL2_DIV0>,
862 <&topckgen CLK_TOP_I2S0_M_SEL>,
863 <&topckgen CLK_TOP_I2S1_M_SEL>,
864 <&topckgen CLK_TOP_I2S2_M_SEL>,
865 <&topckgen CLK_TOP_I2S3_M_SEL>,
866 <&topckgen CLK_TOP_I2S3_B_SEL>;
877 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
878 <&topckgen CLK_TOP_AUD_2_SEL>;
879 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
880 <&topckgen CLK_TOP_APLL2>;
888 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
898 <&topckgen CLK_TOP_AXI_SEL>;
908 <&topckgen CLK_TOP_AXI_SEL>;
918 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
933 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
948 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
991 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
1321 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1397 <&topckgen CLK_TOP_UNIVPLL_D2>,
1398 <&topckgen CLK_TOP_CCI400_SEL>,
1399 <&topckgen CLK_TOP_VDEC_SEL>,
1400 <&topckgen CLK_TOP_VCODECPLL>,
1402 <&topckgen CLK_TOP_VENC_LT_SEL>,
1403 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1412 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1413 <&topckgen CLK_TOP_CCI400_SEL>,
1414 <&topckgen CLK_TOP_VDEC_SEL>,
1417 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1418 <&topckgen CLK_TOP_UNIVPLL_D2>,
1419 <&topckgen CLK_TOP_VCODECPLL>;
1465 clocks = <&topckgen CLK_TOP_VENC_SEL>;
1467 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1468 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1515 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1517 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1519 <&topckgen CLK_TOP_VCODECPLL_370P5>;