Lines Matching refs:infracfg
742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
809 infracfg: syscon@10001000 { label
810 compatible = "mediatek,mt8183-infracfg", "syscon";
861 <&infracfg CLK_INFRA_AUDIO>,
862 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
869 mediatek,infracfg = <&infracfg>;
899 mediatek,infracfg = <&infracfg>;
921 mediatek,infracfg = <&infracfg>;
940 mediatek,infracfg = <&infracfg>;
951 mediatek,infracfg = <&infracfg>;
980 mediatek,infracfg = <&infracfg>;
990 mediatek,infracfg = <&infracfg>;
998 mediatek,infracfg = <&infracfg>;
1024 <&infracfg CLK_INFRA_PMIC_AP>;
1043 clocks = <&infracfg CLK_INFRA_SCPSYS>;
1071 clocks = <&infracfg CLK_INFRA_GCE>;
1079 clocks = <&infracfg CLK_INFRA_AUXADC>;
1090 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
1100 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
1110 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
1120 clocks = <&infracfg CLK_INFRA_I2C6>,
1121 <&infracfg CLK_INFRA_AP_DMA>;
1134 clocks = <&infracfg CLK_INFRA_I2C0>,
1135 <&infracfg CLK_INFRA_AP_DMA>;
1148 clocks = <&infracfg CLK_INFRA_I2C1>,
1149 <&infracfg CLK_INFRA_AP_DMA>,
1150 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1163 clocks = <&infracfg CLK_INFRA_I2C2>,
1164 <&infracfg CLK_INFRA_AP_DMA>,
1165 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1181 <&infracfg CLK_INFRA_SPI0>;
1190 clocks = <&infracfg CLK_INFRA_THERM>;
1202 clocks = <&infracfg CLK_INFRA_THERM>,
1203 <&infracfg CLK_INFRA_AUXADC>;
1205 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>;
1341 <&infracfg CLK_INFRA_DISP_PWM>;
1349 clocks = <&infracfg CLK_INFRA_PWM>,
1350 <&infracfg CLK_INFRA_PWM_HCLK>,
1351 <&infracfg CLK_INFRA_PWM1>,
1352 <&infracfg CLK_INFRA_PWM2>,
1353 <&infracfg CLK_INFRA_PWM3>,
1354 <&infracfg CLK_INFRA_PWM4>;
1364 clocks = <&infracfg CLK_INFRA_I2C3>,
1365 <&infracfg CLK_INFRA_AP_DMA>;
1381 <&infracfg CLK_INFRA_SPI1>;
1391 clocks = <&infracfg CLK_INFRA_I2C4>,
1392 <&infracfg CLK_INFRA_AP_DMA>;
1408 <&infracfg CLK_INFRA_SPI2>;
1421 <&infracfg CLK_INFRA_SPI3>;
1431 clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
1432 <&infracfg CLK_INFRA_AP_DMA>,
1433 <&infracfg CLK_INFRA_I2C1_ARBITER>;
1446 clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
1447 <&infracfg CLK_INFRA_AP_DMA>,
1448 <&infracfg CLK_INFRA_I2C2_ARBITER>;
1461 clocks = <&infracfg CLK_INFRA_I2C5>,
1462 <&infracfg CLK_INFRA_AP_DMA>,
1463 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1476 clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
1477 <&infracfg CLK_INFRA_AP_DMA>,
1478 <&infracfg CLK_INFRA_I2C5_ARBITER>;
1494 <&infracfg CLK_INFRA_SPI4>;
1507 <&infracfg CLK_INFRA_SPI5>;
1517 clocks = <&infracfg CLK_INFRA_I2C7>,
1518 <&infracfg CLK_INFRA_AP_DMA>;
1531 clocks = <&infracfg CLK_INFRA_I2C8>,
1532 <&infracfg CLK_INFRA_AP_DMA>;
1548 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1549 <&infracfg CLK_INFRA_USB>;
1563 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1564 <&infracfg CLK_INFRA_USB>;
1596 <&infracfg CLK_INFRA_AUDIO>,
1597 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
1674 <&infracfg CLK_INFRA_MSDC0>,
1675 <&infracfg CLK_INFRA_MSDC0_SCK>;
1686 <&infracfg CLK_INFRA_MSDC1>,
1687 <&infracfg CLK_INFRA_MSDC1_SCK>;