Lines Matching refs:topckgen
286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
358 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
381 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
404 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
427 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
450 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
473 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
496 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
803 topckgen: syscon@10000000 { label
804 compatible = "mediatek,mt8183-topckgen", "syscon";
860 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
875 clocks = <&topckgen CLK_TOP_MUX_MFG>;
907 clocks = <&topckgen CLK_TOP_MUX_MM>,
929 clocks = <&topckgen CLK_TOP_MUX_CAM>,
947 clocks = <&topckgen CLK_TOP_MUX_IMG>,
970 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
971 <&topckgen CLK_TOP_MUX_DSP>,
988 clocks = <&topckgen CLK_TOP_MUX_DSP1>;
996 clocks = <&topckgen CLK_TOP_MUX_DSP2>;
1023 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
1179 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1180 <&topckgen CLK_TOP_MUX_SPI>,
1340 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
1379 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1380 <&topckgen CLK_TOP_MUX_SPI>,
1406 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1407 <&topckgen CLK_TOP_MUX_SPI>,
1419 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1420 <&topckgen CLK_TOP_MUX_SPI>,
1492 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1493 <&topckgen CLK_TOP_MUX_SPI>,
1505 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1506 <&topckgen CLK_TOP_MUX_SPI>,
1598 <&topckgen CLK_TOP_MUX_AUDIO>,
1599 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
1600 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
1601 <&topckgen CLK_TOP_MUX_AUD_1>,
1602 <&topckgen CLK_TOP_APLL1_CK>,
1603 <&topckgen CLK_TOP_MUX_AUD_2>,
1604 <&topckgen CLK_TOP_APLL2_CK>,
1605 <&topckgen CLK_TOP_MUX_AUD_ENG1>,
1606 <&topckgen CLK_TOP_APLL1_D8>,
1607 <&topckgen CLK_TOP_MUX_AUD_ENG2>,
1608 <&topckgen CLK_TOP_APLL2_D8>,
1609 <&topckgen CLK_TOP_MUX_APLL_I2S0>,
1610 <&topckgen CLK_TOP_MUX_APLL_I2S1>,
1611 <&topckgen CLK_TOP_MUX_APLL_I2S2>,
1612 <&topckgen CLK_TOP_MUX_APLL_I2S3>,
1613 <&topckgen CLK_TOP_MUX_APLL_I2S4>,
1614 <&topckgen CLK_TOP_MUX_APLL_I2S5>,
1615 <&topckgen CLK_TOP_APLL12_DIV0>,
1616 <&topckgen CLK_TOP_APLL12_DIV1>,
1617 <&topckgen CLK_TOP_APLL12_DIV2>,
1618 <&topckgen CLK_TOP_APLL12_DIV3>,
1619 <&topckgen CLK_TOP_APLL12_DIV4>,
1620 <&topckgen CLK_TOP_APLL12_DIVB>,
1621 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
1673 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
1685 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,