Lines Matching refs:topckgen
356 topckgen: syscon@10000000 { label
357 compatible = "mediatek,mt8186-topckgen", "syscon";
408 clocks = <&topckgen CLK_TOP_MFG>;
435 clocks = <&topckgen CLK_TOP_SENINF>,
436 <&topckgen CLK_TOP_SENINF1>;
453 clocks = <&topckgen CLK_TOP_AUDIODSP>,
454 <&topckgen CLK_TOP_ADSP_BUS>;
482 clocks = <&topckgen CLK_TOP_DISP>,
483 <&topckgen CLK_TOP_MDP>,
497 clocks = <&topckgen CLK_TOP_VDEC>,
506 clocks = <&topckgen CLK_TOP_CAM>,
507 <&topckgen CLK_TOP_SENINF>,
508 <&topckgen CLK_TOP_SENINF1>,
509 <&topckgen CLK_TOP_SENINF2>,
510 <&topckgen CLK_TOP_SENINF3>,
511 <&topckgen CLK_TOP_CAMTM>,
533 clocks = <&topckgen CLK_TOP_IMG1>,
549 clocks = <&topckgen CLK_TOP_IPE>,
562 clocks = <&topckgen CLK_TOP_VENC>,
571 clocks = <&topckgen CLK_TOP_WPE>,
638 clocks = <&topckgen CLK_TOP_SPINOR>,
643 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
644 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
809 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
810 <&topckgen CLK_TOP_SPI>,
821 clocks = <&topckgen CLK_TOP_DISP_PWM>,
833 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
834 <&topckgen CLK_TOP_SPI>,
846 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
847 <&topckgen CLK_TOP_SPI>,
859 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
860 <&topckgen CLK_TOP_SPI>,
872 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
873 <&topckgen CLK_TOP_SPI>,
885 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
886 <&topckgen CLK_TOP_SPI>,
927 <&topckgen CLK_TOP_AUDIO>,
928 <&topckgen CLK_TOP_AUD_INTBUS>,
929 <&topckgen CLK_TOP_MAINPLL_D2_D4>,
930 <&topckgen CLK_TOP_AUD_1>,
932 <&topckgen CLK_TOP_AUD_2>,
934 <&topckgen CLK_TOP_AUD_ENGEN1>,
935 <&topckgen CLK_TOP_APLL1_D8>,
936 <&topckgen CLK_TOP_AUD_ENGEN2>,
937 <&topckgen CLK_TOP_APLL2_D8>,
938 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>,
939 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>,
940 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>,
941 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>,
942 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>,
943 <&topckgen CLK_TOP_APLL12_CK_DIV0>,
944 <&topckgen CLK_TOP_APLL12_CK_DIV1>,
945 <&topckgen CLK_TOP_APLL12_CK_DIV2>,
946 <&topckgen CLK_TOP_APLL12_CK_DIV4>,
947 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
948 <&topckgen CLK_TOP_AUDIO_H>,
978 mediatek,topckgen = <&topckgen>;
989 clocks = <&topckgen CLK_TOP_MSDC50_0>,
995 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
1005 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1010 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1011 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1119 clocks = <&topckgen CLK_TOP_DPI>,
1123 assigned-clocks = <&topckgen CLK_TOP_DPI>;
1124 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;