Lines Matching refs:mmsys
460 <&mmsys CLK_MM_SMI_INFRA>,
461 <&mmsys CLK_MM_SMI_COMMON>,
462 <&mmsys CLK_MM_SMI_GALS>,
463 <&mmsys CLK_MM_SMI_IOMMU>;
1275 mmsys: syscon@14000000 { label
1276 compatible = "mediatek,mt8192-mmsys", "syscon";
1289 clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1298 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1299 <&mmsys CLK_MM_SMI_INFRA>,
1300 <&mmsys CLK_MM_SMI_GALS>,
1301 <&mmsys CLK_MM_SMI_GALS>;
1330 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1342 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1353 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1366 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1375 clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1385 clocks = <&mmsys CLK_MM_DISP_AAL0>;
1395 clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1404 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
1414 clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1422 clocks = <&mmsys CLK_MM_DSI0>,
1423 <&mmsys CLK_MM_DSI_DSI0>,
1429 resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;
1442 clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
1454 clocks = <&mmsys CLK_MM_DISP_RDMA4>;
1464 clocks = <&mmsys CLK_MM_DPI_DPI0>,
1465 <&mmsys CLK_MM_DISP_DPI0>,
1480 clocks = <&mmsys CLK_MM_SMI_IOMMU>;