Lines Matching refs:topckgen
341 topckgen: syscon@10000000 { label
342 compatible = "mediatek,mt8192-topckgen", "syscon";
399 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
417 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
459 clocks = <&topckgen CLK_TOP_DISP_SEL>,
473 clocks = <&topckgen CLK_TOP_IPE_SEL>,
486 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
496 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
506 clocks = <&topckgen CLK_TOP_MDP_SEL>,
515 clocks = <&topckgen CLK_TOP_VENC_SEL>,
524 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
547 clocks = <&topckgen CLK_TOP_CAM_SEL>,
612 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
613 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
623 <&topckgen CLK_TOP_SPMI_MST_SEL>;
627 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
628 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
681 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
682 <&topckgen CLK_TOP_SPI_SEL>,
693 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
706 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
707 <&topckgen CLK_TOP_SPI_SEL>,
720 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
721 <&topckgen CLK_TOP_SPI_SEL>,
734 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
735 <&topckgen CLK_TOP_SPI_SEL>,
748 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
749 <&topckgen CLK_TOP_SPI_SEL>,
762 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
763 <&topckgen CLK_TOP_SPI_SEL>,
776 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
777 <&topckgen CLK_TOP_SPI_SEL>,
790 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
791 <&topckgen CLK_TOP_SPI_SEL>,
819 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>,
820 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
821 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
822 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
847 mediatek,topckgen = <&topckgen>;
871 <&topckgen CLK_TOP_AUDIO_SEL>,
872 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
873 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
874 <&topckgen CLK_TOP_AUD_1_SEL>,
875 <&topckgen CLK_TOP_APLL1>,
876 <&topckgen CLK_TOP_AUD_2_SEL>,
877 <&topckgen CLK_TOP_APLL2>,
878 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
879 <&topckgen CLK_TOP_APLL1_D4>,
880 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
881 <&topckgen CLK_TOP_APLL2_D4>,
882 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
883 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
884 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
885 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
886 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
887 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
888 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
889 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
890 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
891 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
892 <&topckgen CLK_TOP_APLL12_DIV0>,
893 <&topckgen CLK_TOP_APLL12_DIV1>,
894 <&topckgen CLK_TOP_APLL12_DIV2>,
895 <&topckgen CLK_TOP_APLL12_DIV3>,
896 <&topckgen CLK_TOP_APLL12_DIV4>,
897 <&topckgen CLK_TOP_APLL12_DIVB>,
898 <&topckgen CLK_TOP_APLL12_DIV5>,
899 <&topckgen CLK_TOP_APLL12_DIV6>,
900 <&topckgen CLK_TOP_APLL12_DIV7>,
901 <&topckgen CLK_TOP_APLL12_DIV8>,
902 <&topckgen CLK_TOP_APLL12_DIV9>,
903 <&topckgen CLK_TOP_AUDIO_H_SEL>,
979 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>;
980 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>;
1003 clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
1007 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
1241 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
1257 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
1590 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1591 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;