Lines Matching refs:topckgen
389 topckgen: syscon@10000000 { label
390 compatible = "mediatek,mt8195-topckgen", "syscon";
485 clocks = <&topckgen CLK_TOP_VPP>,
486 <&topckgen CLK_TOP_CAM>,
487 <&topckgen CLK_TOP_CCU>,
488 <&topckgen CLK_TOP_IMG>,
489 <&topckgen CLK_TOP_VENC>,
490 <&topckgen CLK_TOP_VDEC>,
491 <&topckgen CLK_TOP_WPE_VPP>,
492 <&topckgen CLK_TOP_CFG_VPP0>,
541 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
558 clocks = <&topckgen CLK_TOP_CFG_VPP1>,
603 clocks = <&topckgen CLK_TOP_CFG_VDO1>,
628 clocks = <&topckgen CLK_TOP_HDMI_APB>;
651 clocks = <&topckgen CLK_TOP_IPE>,
716 clocks = <&topckgen CLK_TOP_SENINF>,
717 <&topckgen CLK_TOP_SENINF2>;
731 clocks = <&topckgen CLK_TOP_ADSP>,
732 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
741 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
742 <&topckgen CLK_TOP_AUD_INTBUS>,
743 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
783 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
784 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
794 <&topckgen CLK_TOP_SPMI_M_MST>;
798 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
799 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
850 clocks = <&topckgen CLK_TOP_ADSP>,
852 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
853 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
855 <&topckgen CLK_TOP_AUDIO_H>;
885 mediatek,topckgen = <&topckgen>;
893 <&topckgen CLK_TOP_APLL12_DIV0>,
894 <&topckgen CLK_TOP_APLL12_DIV1>,
895 <&topckgen CLK_TOP_APLL12_DIV2>,
896 <&topckgen CLK_TOP_APLL12_DIV3>,
897 <&topckgen CLK_TOP_APLL12_DIV9>,
898 <&topckgen CLK_TOP_A1SYS_HP>,
899 <&topckgen CLK_TOP_AUD_INTBUS>,
900 <&topckgen CLK_TOP_AUDIO_H>,
901 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
902 <&topckgen CLK_TOP_DPTX_MCK>,
903 <&topckgen CLK_TOP_I2SO1_MCK>,
904 <&topckgen CLK_TOP_I2SO2_MCK>,
905 <&topckgen CLK_TOP_I2SI1_MCK>,
906 <&topckgen CLK_TOP_I2SI2_MCK>,
1014 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1015 <&topckgen CLK_TOP_SPI>,
1028 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1029 <&topckgen CLK_TOP_SPI>,
1042 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1043 <&topckgen CLK_TOP_SPI>,
1056 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1057 <&topckgen CLK_TOP_SPI>,
1070 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1071 <&topckgen CLK_TOP_SPI>,
1084 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1085 <&topckgen CLK_TOP_SPI>,
1097 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1098 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1108 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1109 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1126 <&topckgen CLK_TOP_SNPS_ETH_250M>,
1127 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1128 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1130 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1131 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1132 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1133 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1134 <&topckgen CLK_TOP_ETHPLL_D8>,
1135 <&topckgen CLK_TOP_ETHPLL_D10>;
1214 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1215 <&topckgen CLK_TOP_SSUSB_XHCI>;
1216 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1217 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1219 <&topckgen CLK_TOP_SSUSB_REF>,
1236 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1249 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1253 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1254 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1264 clocks = <&topckgen CLK_TOP_MSDC30_2>,
1268 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1269 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1281 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1282 <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1283 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1284 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1286 <&topckgen CLK_TOP_SSUSB_P1_REF>,
1305 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1306 <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1307 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1308 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1310 <&topckgen CLK_TOP_SSUSB_P2_REF>,
1329 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1330 <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1331 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1332 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1334 <&topckgen CLK_TOP_SSUSB_P3_REF>,
1371 assigned-clocks = <&topckgen CLK_TOP_TL>;
1372 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1424 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1425 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1454 clocks = <&topckgen CLK_TOP_SPINOR>,
1556 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1571 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1719 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1728 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1747 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1756 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
2297 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2298 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;