Lines Matching refs:bpmp
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
61 resets = <&bpmp TEGRA186_RESET_EQOS>;
79 resets = <&bpmp TEGRA186_RESET_GPCDMA>;
123 clocks = <&bpmp TEGRA186_CLK_APE>,
124 <&bpmp TEGRA186_CLK_APB2APE>;
126 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
135 clocks = <&bpmp TEGRA186_CLK_AHUB>;
137 assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
148 clocks = <&bpmp TEGRA186_CLK_I2S1>,
149 <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
151 assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
152 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
162 clocks = <&bpmp TEGRA186_CLK_I2S2>,
163 <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
165 assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
166 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
176 clocks = <&bpmp TEGRA186_CLK_I2S3>,
177 <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
179 assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
180 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
190 clocks = <&bpmp TEGRA186_CLK_I2S4>,
191 <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
193 assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
194 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
204 clocks = <&bpmp TEGRA186_CLK_I2S5>,
205 <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
207 assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
208 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
218 clocks = <&bpmp TEGRA186_CLK_I2S6>,
219 <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
221 assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
222 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
327 clocks = <&bpmp TEGRA186_CLK_DMIC1>;
329 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
330 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
339 clocks = <&bpmp TEGRA186_CLK_DMIC2>;
341 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
342 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
351 clocks = <&bpmp TEGRA186_CLK_DMIC3>;
353 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
354 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
363 clocks = <&bpmp TEGRA186_CLK_DMIC4>;
365 assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
366 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
375 clocks = <&bpmp TEGRA186_CLK_DSPK1>;
377 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
378 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
387 clocks = <&bpmp TEGRA186_CLK_DSPK2>;
389 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
390 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
534 clocks = <&bpmp TEGRA186_CLK_AHUB>;
548 clocks = <&bpmp TEGRA186_CLK_APE>;
582 clocks = <&bpmp TEGRA186_CLK_EMC>;
587 nvidia,bpmp = <&bpmp>;
612 clocks = <&bpmp TEGRA186_CLK_UARTA>;
614 resets = <&bpmp TEGRA186_RESET_UARTA>;
624 clocks = <&bpmp TEGRA186_CLK_UARTB>;
626 resets = <&bpmp TEGRA186_RESET_UARTB>;
636 clocks = <&bpmp TEGRA186_CLK_UARTD>;
638 resets = <&bpmp TEGRA186_RESET_UARTD>;
648 clocks = <&bpmp TEGRA186_CLK_UARTE>;
650 resets = <&bpmp TEGRA186_RESET_UARTE>;
660 clocks = <&bpmp TEGRA186_CLK_UARTF>;
662 resets = <&bpmp TEGRA186_RESET_UARTF>;
673 clocks = <&bpmp TEGRA186_CLK_I2C1>;
675 resets = <&bpmp TEGRA186_RESET_I2C1>;
688 clocks = <&bpmp TEGRA186_CLK_I2C3>;
690 resets = <&bpmp TEGRA186_RESET_I2C3>;
704 clocks = <&bpmp TEGRA186_CLK_I2C4>;
706 resets = <&bpmp TEGRA186_RESET_I2C4>;
723 clocks = <&bpmp TEGRA186_CLK_I2C5>;
725 resets = <&bpmp TEGRA186_RESET_I2C5>;
737 clocks = <&bpmp TEGRA186_CLK_I2C6>;
739 resets = <&bpmp TEGRA186_RESET_I2C6>;
755 clocks = <&bpmp TEGRA186_CLK_I2C7>;
757 resets = <&bpmp TEGRA186_RESET_I2C7>;
770 clocks = <&bpmp TEGRA186_CLK_I2C9>;
772 resets = <&bpmp TEGRA186_RESET_I2C9>;
782 clocks = <&bpmp TEGRA186_CLK_PWM1>;
783 resets = <&bpmp TEGRA186_RESET_PWM1>;
792 clocks = <&bpmp TEGRA186_CLK_PWM2>;
793 resets = <&bpmp TEGRA186_RESET_PWM2>;
802 clocks = <&bpmp TEGRA186_CLK_PWM3>;
803 resets = <&bpmp TEGRA186_RESET_PWM3>;
812 clocks = <&bpmp TEGRA186_CLK_PWM5>;
813 resets = <&bpmp TEGRA186_RESET_PWM5>;
822 clocks = <&bpmp TEGRA186_CLK_PWM6>;
823 resets = <&bpmp TEGRA186_RESET_PWM6>;
832 clocks = <&bpmp TEGRA186_CLK_PWM7>;
833 resets = <&bpmp TEGRA186_RESET_PWM7>;
842 clocks = <&bpmp TEGRA186_CLK_PWM8>;
843 resets = <&bpmp TEGRA186_RESET_PWM8>;
853 clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
854 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
856 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
873 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
874 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
875 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
883 clocks = <&bpmp TEGRA186_CLK_SDMMC2>,
884 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
886 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
908 clocks = <&bpmp TEGRA186_CLK_SDMMC3>,
909 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
911 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
935 clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
936 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
938 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
939 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
940 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
941 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
968 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>;
974 clocks = <&bpmp TEGRA186_CLK_SATA>,
975 <&bpmp TEGRA186_CLK_SATA_OOB>;
977 assigned-clocks = <&bpmp TEGRA186_CLK_SATA>,
978 <&bpmp TEGRA186_CLK_SATA_OOB>;
979 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,
980 <&bpmp TEGRA186_CLK_PLLP>;
983 resets = <&bpmp TEGRA186_RESET_SATA>,
984 <&bpmp TEGRA186_RESET_SATACOLD>;
993 clocks = <&bpmp TEGRA186_CLK_HDA>,
994 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
995 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
997 resets = <&bpmp TEGRA186_RESET_HDA>,
998 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
999 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
1001 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1016 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
1023 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
1046 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
1118 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
1119 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
1120 <&bpmp TEGRA186_CLK_XUSB_SS>,
1121 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1122 <&bpmp TEGRA186_CLK_CLK_M>,
1123 <&bpmp TEGRA186_CLK_XUSB_FS>,
1124 <&bpmp TEGRA186_CLK_PLLU>,
1125 <&bpmp TEGRA186_CLK_CLK_M>,
1126 <&bpmp TEGRA186_CLK_PLLE>;
1130 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
1131 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1150 clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>,
1151 <&bpmp TEGRA186_CLK_XUSB_SS>,
1152 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
1153 <&bpmp TEGRA186_CLK_XUSB_FS>;
1159 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>,
1160 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
1169 clocks = <&bpmp TEGRA186_CLK_FUSE>;
1190 clocks = <&bpmp TEGRA186_CLK_CEC>;
1210 clocks = <&bpmp TEGRA186_CLK_I2C2>;
1212 resets = <&bpmp TEGRA186_RESET_I2C2>;
1225 clocks = <&bpmp TEGRA186_CLK_I2C8>;
1227 resets = <&bpmp TEGRA186_RESET_I2C8>;
1239 clocks = <&bpmp TEGRA186_CLK_UARTC>;
1241 resets = <&bpmp TEGRA186_RESET_UARTC>;
1251 clocks = <&bpmp TEGRA186_CLK_UARTG>;
1253 resets = <&bpmp TEGRA186_RESET_UARTG>;
1263 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
1283 clocks = <&bpmp TEGRA186_CLK_PWM4>;
1284 resets = <&bpmp TEGRA186_RESET_PWM4>;
1336 nvidia,bpmp = <&bpmp>;
1341 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
1367 clocks = <&bpmp TEGRA186_CLK_PCIE>,
1368 <&bpmp TEGRA186_CLK_AFI>,
1369 <&bpmp TEGRA186_CLK_PLLE>;
1372 resets = <&bpmp TEGRA186_RESET_PCIE>,
1373 <&bpmp TEGRA186_RESET_AFI>,
1374 <&bpmp TEGRA186_RESET_PCIEXCLK>;
1510 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
1512 resets = <&bpmp TEGRA186_RESET_HOST1X>;
1539 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
1540 <&bpmp TEGRA186_CLK_PLLDP>;
1542 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
1546 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1572 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
1573 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
1574 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
1575 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
1576 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
1577 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
1578 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
1581 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
1582 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
1583 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
1587 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1598 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
1600 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
1603 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1617 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
1619 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
1622 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
1636 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1638 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1641 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1656 clocks = <&bpmp TEGRA186_CLK_DSI>,
1657 <&bpmp TEGRA186_CLK_DSIA_LP>,
1658 <&bpmp TEGRA186_CLK_PLLD>;
1660 resets = <&bpmp TEGRA186_RESET_DSI>;
1664 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1671 clocks = <&bpmp TEGRA186_CLK_VIC>;
1673 resets = <&bpmp TEGRA186_RESET_VIC>;
1676 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1686 clocks = <&bpmp TEGRA186_CLK_NVJPG>;
1688 resets = <&bpmp TEGRA186_RESET_NVJPG>;
1691 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
1702 clocks = <&bpmp TEGRA186_CLK_DSIB>,
1703 <&bpmp TEGRA186_CLK_DSIB_LP>,
1704 <&bpmp TEGRA186_CLK_PLLD>;
1706 resets = <&bpmp TEGRA186_RESET_DSIB>;
1710 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1716 clocks = <&bpmp TEGRA186_CLK_NVDEC>;
1718 resets = <&bpmp TEGRA186_RESET_NVDEC>;
1721 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
1732 clocks = <&bpmp TEGRA186_CLK_NVENC>;
1734 resets = <&bpmp TEGRA186_RESET_NVENC>;
1737 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
1748 clocks = <&bpmp TEGRA186_CLK_SOR0>,
1749 <&bpmp TEGRA186_CLK_SOR0_OUT>,
1750 <&bpmp TEGRA186_CLK_PLLD2>,
1751 <&bpmp TEGRA186_CLK_PLLDP>,
1752 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1753 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1756 resets = <&bpmp TEGRA186_RESET_SOR0>;
1764 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1772 clocks = <&bpmp TEGRA186_CLK_SOR1>,
1773 <&bpmp TEGRA186_CLK_SOR1_OUT>,
1774 <&bpmp TEGRA186_CLK_PLLD3>,
1775 <&bpmp TEGRA186_CLK_PLLDP>,
1776 <&bpmp TEGRA186_CLK_SOR_SAFE>,
1777 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1780 resets = <&bpmp TEGRA186_RESET_SOR1>;
1788 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1796 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1797 <&bpmp TEGRA186_CLK_PLLDP>;
1799 resets = <&bpmp TEGRA186_RESET_DPAUX>;
1803 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1829 resets = <&bpmp TEGRA186_RESET_DSI>;
1838 clocks = <&bpmp TEGRA186_CLK_DSIC>,
1839 <&bpmp TEGRA186_CLK_DSIC_LP>,
1840 <&bpmp TEGRA186_CLK_PLLD>;
1842 resets = <&bpmp TEGRA186_RESET_DSIC>;
1846 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1853 clocks = <&bpmp TEGRA186_CLK_DSID>,
1854 <&bpmp TEGRA186_CLK_DSID_LP>,
1855 <&bpmp TEGRA186_CLK_PLLD>;
1857 resets = <&bpmp TEGRA186_RESET_DSID>;
1861 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1873 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1874 <&bpmp TEGRA186_CLK_GPU>;
1876 resets = <&bpmp TEGRA186_RESET_GPU>;
1880 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1898 label = "cpu-bpmp-tx";
1904 label = "cpu-bpmp-rx";
1909 bpmp: bpmp { label
1910 compatible = "nvidia,tegra186-bpmp";
1925 compatible = "nvidia,tegra186-bpmp-i2c";
1926 nvidia,bpmp-bus-id = <5>;
1933 compatible = "nvidia,tegra186-bpmp-thermal";
2058 clocks = <&bpmp TEGRA186_CLK_PLLA>,
2059 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
2061 assigned-clocks = <&bpmp TEGRA186_CLK_PLLA>,
2062 <&bpmp TEGRA186_CLK_PLL_A_OUT0>,
2063 <&bpmp TEGRA186_CLK_AUD_MCLK>;
2065 <&bpmp TEGRA186_CLK_PLLA>,
2066 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;