Lines Matching refs:bpmp
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
148 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
149 <&bpmp TEGRA194_CLK_EQOS_AXI>,
150 <&bpmp TEGRA194_CLK_EQOS_RX>,
151 <&bpmp TEGRA194_CLK_EQOS_TX>,
152 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
154 resets = <&bpmp TEGRA194_RESET_EQOS>;
173 resets = <&bpmp TEGRA194_RESET_GPCDMA>;
217 clocks = <&bpmp TEGRA194_CLK_APE>,
218 <&bpmp TEGRA194_CLK_APB2APE>;
220 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
231 clocks = <&bpmp TEGRA194_CLK_AHUB>;
233 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
245 clocks = <&bpmp TEGRA194_CLK_I2S1>,
246 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
248 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
249 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
259 clocks = <&bpmp TEGRA194_CLK_I2S2>,
260 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
262 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
263 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
273 clocks = <&bpmp TEGRA194_CLK_I2S3>,
274 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
276 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
277 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
287 clocks = <&bpmp TEGRA194_CLK_I2S4>,
288 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
290 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
291 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
301 clocks = <&bpmp TEGRA194_CLK_I2S5>,
302 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
304 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
305 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
315 clocks = <&bpmp TEGRA194_CLK_I2S6>,
316 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
318 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
319 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
421 clocks = <&bpmp TEGRA194_CLK_DMIC1>;
423 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
424 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
434 clocks = <&bpmp TEGRA194_CLK_DMIC2>;
436 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
437 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
447 clocks = <&bpmp TEGRA194_CLK_DMIC3>;
449 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
450 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
460 clocks = <&bpmp TEGRA194_CLK_DMIC4>;
462 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
463 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
473 clocks = <&bpmp TEGRA194_CLK_DSPK1>;
475 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
476 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
486 clocks = <&bpmp TEGRA194_CLK_DSPK2>;
488 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
489 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
641 clocks = <&bpmp TEGRA194_CLK_AHUB>;
656 clocks = <&bpmp TEGRA194_CLK_APE>;
717 clocks = <&bpmp TEGRA194_CLK_EMC>;
722 nvidia,bpmp = <&bpmp>;
747 clocks = <&bpmp TEGRA194_CLK_UARTA>;
749 resets = <&bpmp TEGRA194_RESET_UARTA>;
759 clocks = <&bpmp TEGRA194_CLK_UARTB>;
761 resets = <&bpmp TEGRA194_RESET_UARTB>;
771 clocks = <&bpmp TEGRA194_CLK_UARTD>;
773 resets = <&bpmp TEGRA194_RESET_UARTD>;
783 clocks = <&bpmp TEGRA194_CLK_UARTE>;
785 resets = <&bpmp TEGRA194_RESET_UARTE>;
795 clocks = <&bpmp TEGRA194_CLK_UARTF>;
797 resets = <&bpmp TEGRA194_RESET_UARTF>;
808 clocks = <&bpmp TEGRA194_CLK_I2C1>;
810 resets = <&bpmp TEGRA194_RESET_I2C1>;
822 clocks = <&bpmp TEGRA194_CLK_UARTH>;
824 resets = <&bpmp TEGRA194_RESET_UARTH>;
835 clocks = <&bpmp TEGRA194_CLK_I2C3>;
837 resets = <&bpmp TEGRA194_RESET_I2C3>;
851 clocks = <&bpmp TEGRA194_CLK_I2C4>;
853 resets = <&bpmp TEGRA194_RESET_I2C4>;
870 clocks = <&bpmp TEGRA194_CLK_I2C6>;
872 resets = <&bpmp TEGRA194_RESET_I2C6>;
889 clocks = <&bpmp TEGRA194_CLK_I2C7>;
891 resets = <&bpmp TEGRA194_RESET_I2C7>;
908 clocks = <&bpmp TEGRA194_CLK_I2C9>;
910 resets = <&bpmp TEGRA194_RESET_I2C9>;
926 clocks = <&bpmp TEGRA194_CLK_QSPI0>,
927 <&bpmp TEGRA194_CLK_QSPI0_PM>;
929 resets = <&bpmp TEGRA194_RESET_QSPI0>;
937 clocks = <&bpmp TEGRA194_CLK_PWM1>;
938 resets = <&bpmp TEGRA194_RESET_PWM1>;
948 clocks = <&bpmp TEGRA194_CLK_PWM2>;
949 resets = <&bpmp TEGRA194_RESET_PWM2>;
959 clocks = <&bpmp TEGRA194_CLK_PWM3>;
960 resets = <&bpmp TEGRA194_RESET_PWM3>;
970 clocks = <&bpmp TEGRA194_CLK_PWM5>;
971 resets = <&bpmp TEGRA194_RESET_PWM5>;
981 clocks = <&bpmp TEGRA194_CLK_PWM6>;
982 resets = <&bpmp TEGRA194_RESET_PWM6>;
992 clocks = <&bpmp TEGRA194_CLK_PWM7>;
993 resets = <&bpmp TEGRA194_RESET_PWM7>;
1003 clocks = <&bpmp TEGRA194_CLK_PWM8>;
1004 resets = <&bpmp TEGRA194_RESET_PWM8>;
1016 clocks = <&bpmp TEGRA194_CLK_QSPI1>,
1017 <&bpmp TEGRA194_CLK_QSPI1_PM>;
1019 resets = <&bpmp TEGRA194_RESET_QSPI1>;
1027 clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1028 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1030 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>,
1031 <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1033 <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1034 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1035 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
1066 clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1067 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1069 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>,
1070 <&bpmp TEGRA194_CLK_PLLC4_MUXED>;
1072 <&bpmp TEGRA194_CLK_PLLC4_MUXED>,
1073 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>;
1074 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
1106 clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1107 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>;
1109 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
1110 <&bpmp TEGRA194_CLK_PLLC4>;
1112 <&bpmp TEGRA194_CLK_PLLC4>;
1113 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
1143 clocks = <&bpmp TEGRA194_CLK_HDA>,
1144 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>,
1145 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>;
1147 resets = <&bpmp TEGRA194_RESET_HDA>,
1148 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
1150 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1165 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
1172 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
1272 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
1273 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1274 <&bpmp TEGRA194_CLK_XUSB_SS>,
1275 <&bpmp TEGRA194_CLK_XUSB_FS>;
1281 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
1282 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1298 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
1299 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
1300 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
1301 <&bpmp TEGRA194_CLK_XUSB_SS>,
1302 <&bpmp TEGRA194_CLK_CLK_M>,
1303 <&bpmp TEGRA194_CLK_XUSB_FS>,
1304 <&bpmp TEGRA194_CLK_UTMIPLL>,
1305 <&bpmp TEGRA194_CLK_CLK_M>,
1306 <&bpmp TEGRA194_CLK_PLLE>;
1316 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
1317 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
1327 clocks = <&bpmp TEGRA194_CLK_FUSE>;
1348 clocks = <&bpmp TEGRA194_CLK_CEC>;
1592 clocks = <&bpmp TEGRA194_CLK_I2C2>;
1594 resets = <&bpmp TEGRA194_RESET_I2C2>;
1607 clocks = <&bpmp TEGRA194_CLK_I2C8>;
1609 resets = <&bpmp TEGRA194_RESET_I2C8>;
1621 clocks = <&bpmp TEGRA194_CLK_UARTC>;
1623 resets = <&bpmp TEGRA194_RESET_UARTC>;
1633 clocks = <&bpmp TEGRA194_CLK_UARTG>;
1635 resets = <&bpmp TEGRA194_RESET_UARTG>;
1645 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
1677 clocks = <&bpmp TEGRA194_CLK_PWM4>;
1678 resets = <&bpmp TEGRA194_RESET_PWM4>;
1726 bpmp-noc@d600000 {
1727 compatible = "nvidia,tegra194-bpmp-noc";
1898 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1900 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1925 clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
1927 resets = <&bpmp TEGRA194_RESET_NVDEC1>;
1930 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
1944 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1945 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1946 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1947 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1948 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1949 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1950 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1953 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1954 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1958 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1968 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1970 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1973 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1986 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1988 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1991 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
2004 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
2006 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
2009 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2022 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
2024 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
2027 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
2041 clocks = <&bpmp TEGRA194_CLK_VIC>;
2043 resets = <&bpmp TEGRA194_RESET_VIC>;
2046 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
2057 clocks = <&bpmp TEGRA194_CLK_NVJPG>;
2059 resets = <&bpmp TEGRA194_RESET_NVJPG>;
2062 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
2073 clocks = <&bpmp TEGRA194_CLK_NVDEC>;
2075 resets = <&bpmp TEGRA194_RESET_NVDEC>;
2078 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
2092 clocks = <&bpmp TEGRA194_CLK_NVENC>;
2094 resets = <&bpmp TEGRA194_RESET_NVENC>;
2097 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
2112 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
2113 <&bpmp TEGRA194_CLK_PLLDP>;
2115 resets = <&bpmp TEGRA194_RESET_DPAUX>;
2119 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2146 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
2147 <&bpmp TEGRA194_CLK_PLLDP>;
2149 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
2153 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2180 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
2181 <&bpmp TEGRA194_CLK_PLLDP>;
2183 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
2187 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2214 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
2215 <&bpmp TEGRA194_CLK_PLLDP>;
2217 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
2221 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2247 clocks = <&bpmp TEGRA194_CLK_NVENC1>;
2249 resets = <&bpmp TEGRA194_RESET_NVENC1>;
2252 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
2267 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
2268 <&bpmp TEGRA194_CLK_SOR0_OUT>,
2269 <&bpmp TEGRA194_CLK_PLLD>,
2270 <&bpmp TEGRA194_CLK_PLLDP>,
2271 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2272 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
2275 resets = <&bpmp TEGRA194_RESET_SOR0>;
2283 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2291 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
2292 <&bpmp TEGRA194_CLK_SOR1_OUT>,
2293 <&bpmp TEGRA194_CLK_PLLD2>,
2294 <&bpmp TEGRA194_CLK_PLLDP>,
2295 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2296 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
2299 resets = <&bpmp TEGRA194_RESET_SOR1>;
2307 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2315 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
2316 <&bpmp TEGRA194_CLK_SOR2_OUT>,
2317 <&bpmp TEGRA194_CLK_PLLD3>,
2318 <&bpmp TEGRA194_CLK_PLLDP>,
2319 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2320 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
2323 resets = <&bpmp TEGRA194_RESET_SOR2>;
2331 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2339 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
2340 <&bpmp TEGRA194_CLK_SOR3_OUT>,
2341 <&bpmp TEGRA194_CLK_PLLD4>,
2342 <&bpmp TEGRA194_CLK_PLLDP>,
2343 <&bpmp TEGRA194_CLK_SOR_SAFE>,
2344 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
2347 resets = <&bpmp TEGRA194_RESET_SOR3>;
2355 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
2362 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2377 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
2380 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
2381 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
2392 nvidia,bpmp = <&bpmp 1>;
2414 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2429 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
2432 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
2433 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
2444 nvidia,bpmp = <&bpmp 2>;
2466 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
2481 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
2484 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
2485 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
2496 nvidia,bpmp = <&bpmp 3>;
2518 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2533 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2536 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2537 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2548 nvidia,bpmp = <&bpmp 4>;
2570 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
2583 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
2586 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
2587 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
2593 nvidia,bpmp = <&bpmp 4>;
2609 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2624 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2627 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2628 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2639 nvidia,bpmp = <&bpmp 0>;
2661 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
2674 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
2677 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
2678 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
2684 nvidia,bpmp = <&bpmp 0>;
2700 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2718 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2721 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2722 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2729 nvidia,bpmp = <&bpmp 5>;
2755 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
2771 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
2774 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
2775 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
2781 nvidia,bpmp = <&bpmp 5>;
2802 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
2803 <&bpmp TEGRA194_CLK_GPU_PWR>,
2804 <&bpmp TEGRA194_CLK_FUSE>;
2806 resets = <&bpmp TEGRA194_RESET_GPU>;
2810 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
2842 label = "cpu-bpmp-tx";
2848 label = "cpu-bpmp-rx";
2853 bpmp: bpmp { label
2854 compatible = "nvidia,tegra186-bpmp";
2869 compatible = "nvidia,tegra186-bpmp-i2c";
2870 nvidia,bpmp-bus-id = <5>;
2876 compatible = "nvidia,tegra186-bpmp-thermal";
2883 nvidia,bpmp = <&bpmp>;
3121 clocks = <&bpmp TEGRA194_CLK_PLLA>,
3122 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3124 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>,
3125 <&bpmp TEGRA194_CLK_PLLA_OUT0>,
3126 <&bpmp TEGRA194_CLK_AUD_MCLK>;
3128 <&bpmp TEGRA194_CLK_PLLA>,
3129 <&bpmp TEGRA194_CLK_PLLA_OUT0>;
3140 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>;
3145 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>;
3150 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>;
3155 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
3160 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>;
3165 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;