Lines Matching refs:cpg
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
44 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
54 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
64 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
133 clocks = <&cpg CPG_MOD 402>;
135 resets = <&cpg 402>;
149 clocks = <&cpg CPG_MOD 912>;
151 resets = <&cpg 912>;
164 clocks = <&cpg CPG_MOD 911>;
166 resets = <&cpg 911>;
179 clocks = <&cpg CPG_MOD 910>;
181 resets = <&cpg 910>;
194 clocks = <&cpg CPG_MOD 909>;
196 resets = <&cpg 909>;
209 clocks = <&cpg CPG_MOD 908>;
211 resets = <&cpg 908>;
224 clocks = <&cpg CPG_MOD 907>;
226 resets = <&cpg 907>;
240 clocks = <&cpg CPG_MOD 303>;
243 resets = <&cpg 303>;
259 clocks = <&cpg CPG_MOD 302>;
262 resets = <&cpg 302>;
278 clocks = <&cpg CPG_MOD 301>;
281 resets = <&cpg 301>;
297 clocks = <&cpg CPG_MOD 300>;
300 resets = <&cpg 300>;
304 cpg: clock-controller@e6150000 { label
305 compatible = "renesas,r8a77980-cpg-mssr";
332 clocks = <&cpg CPG_MOD 522>;
334 resets = <&cpg 522>;
349 clocks = <&cpg CPG_MOD 407>;
351 resets = <&cpg 407>;
360 clocks = <&cpg CPG_MOD 125>;
363 resets = <&cpg 125>;
373 clocks = <&cpg CPG_MOD 124>;
376 resets = <&cpg 124>;
386 clocks = <&cpg CPG_MOD 123>;
389 resets = <&cpg 123>;
399 clocks = <&cpg CPG_MOD 122>;
402 resets = <&cpg 122>;
412 clocks = <&cpg CPG_MOD 121>;
415 resets = <&cpg 121>;
424 clocks = <&cpg CPG_MOD 931>;
426 resets = <&cpg 931>;
441 clocks = <&cpg CPG_MOD 930>;
443 resets = <&cpg 930>;
458 clocks = <&cpg CPG_MOD 929>;
460 resets = <&cpg 929>;
475 clocks = <&cpg CPG_MOD 928>;
477 resets = <&cpg 928>;
489 clocks = <&cpg CPG_MOD 927>;
491 resets = <&cpg 927>;
503 clocks = <&cpg CPG_MOD 919>;
505 resets = <&cpg 919>;
521 clocks = <&cpg CPG_MOD 520>,
522 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
529 resets = <&cpg 520>;
539 clocks = <&cpg CPG_MOD 519>,
540 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
547 resets = <&cpg 519>;
557 clocks = <&cpg CPG_MOD 518>,
558 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
565 resets = <&cpg 518>;
575 clocks = <&cpg CPG_MOD 517>,
576 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
583 resets = <&cpg 517>;
591 clocks = <&cpg CPG_MOD 319>;
593 resets = <&cpg 319>;
604 clocks = <&cpg CPG_MOD 914>,
605 <&cpg CPG_CORE R8A77980_CLK_CANFD>,
608 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
611 resets = <&cpg 914>;
659 clocks = <&cpg CPG_MOD 812>;
662 resets = <&cpg 812>;
676 clocks = <&cpg CPG_MOD 523>;
678 resets = <&cpg 523>;
686 clocks = <&cpg CPG_MOD 523>;
688 resets = <&cpg 523>;
696 clocks = <&cpg CPG_MOD 523>;
698 resets = <&cpg 523>;
706 clocks = <&cpg CPG_MOD 523>;
708 resets = <&cpg 523>;
716 clocks = <&cpg CPG_MOD 523>;
718 resets = <&cpg 523>;
728 clocks = <&cpg CPG_MOD 207>,
729 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
736 resets = <&cpg 207>;
746 clocks = <&cpg CPG_MOD 206>,
747 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
754 resets = <&cpg 206>;
764 clocks = <&cpg CPG_MOD 204>,
765 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
772 resets = <&cpg 204>;
782 clocks = <&cpg CPG_MOD 203>,
783 <&cpg CPG_CORE R8A77980_CLK_S3D1>,
790 resets = <&cpg 203>;
798 clocks = <&cpg CPG_MOD 304>;
800 resets = <&cpg 304>;
810 clocks = <&cpg CPG_MOD 211>;
812 resets = <&cpg 211>;
823 clocks = <&cpg CPG_MOD 210>;
825 resets = <&cpg 210>;
836 clocks = <&cpg CPG_MOD 209>;
838 resets = <&cpg 209>;
849 clocks = <&cpg CPG_MOD 208>;
851 resets = <&cpg 208>;
861 clocks = <&cpg CPG_MOD 811>;
863 resets = <&cpg 811>;
889 clocks = <&cpg CPG_MOD 810>;
893 resets = <&cpg 810>;
917 clocks = <&cpg CPG_MOD 809>;
919 resets = <&cpg 809>;
945 clocks = <&cpg CPG_MOD 808>;
947 resets = <&cpg 808>;
973 clocks = <&cpg CPG_MOD 807>;
975 resets = <&cpg 807>;
1001 clocks = <&cpg CPG_MOD 806>;
1003 resets = <&cpg 806>;
1029 clocks = <&cpg CPG_MOD 805>;
1031 resets = <&cpg 805>;
1057 clocks = <&cpg CPG_MOD 804>;
1059 resets = <&cpg 804>;
1085 clocks = <&cpg CPG_MOD 628>;
1087 resets = <&cpg 628>;
1096 clocks = <&cpg CPG_MOD 627>;
1098 resets = <&cpg 627>;
1107 clocks = <&cpg CPG_MOD 625>;
1109 resets = <&cpg 625>;
1118 clocks = <&cpg CPG_MOD 618>;
1120 resets = <&cpg 618>;
1129 clocks = <&cpg CPG_MOD 612>;
1131 resets = <&cpg 612>;
1140 clocks = <&cpg CPG_MOD 608>;
1142 resets = <&cpg 608>;
1151 clocks = <&cpg CPG_MOD 605>;
1153 resets = <&cpg 605>;
1162 clocks = <&cpg CPG_MOD 604>;
1164 resets = <&cpg 604>;
1195 clocks = <&cpg CPG_MOD 218>;
1198 resets = <&cpg 218>;
1237 clocks = <&cpg CPG_MOD 217>;
1240 resets = <&cpg 217>;
1257 clocks = <&cpg CPG_MOD 813>;
1259 resets = <&cpg 813>;
1335 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>;
1338 resets = <&cpg 314>;
1352 clocks = <&cpg CPG_MOD 917>;
1354 resets = <&cpg 917>;
1371 clocks = <&cpg CPG_MOD 408>;
1374 resets = <&cpg 408>;
1396 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1399 resets = <&cpg 319>;
1409 clocks = <&cpg CPG_MOD 623>;
1411 resets = <&cpg 623>;
1418 clocks = <&cpg CPG_MOD 603>;
1420 resets = <&cpg 603>;
1427 clocks = <&cpg CPG_MOD 716>;
1429 resets = <&cpg 716>;
1470 clocks = <&cpg CPG_MOD 715>;
1472 resets = <&cpg 715>;
1513 clocks = <&cpg CPG_MOD 724>;
1516 resets = <&cpg 724>;
1542 clocks = <&cpg CPG_MOD 727>;
1544 resets = <&cpg 727>;