Lines Matching refs:cpg
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
86 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
87 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
90 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
93 power-domains = <&cpg>;
107 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
108 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
111 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
114 power-domains = <&cpg>;
128 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
129 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
132 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
135 power-domains = <&cpg>;
149 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
150 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
153 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
156 power-domains = <&cpg>;
168 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
169 resets = <&cpg R9A07G043_RSPI0_RST>;
172 power-domains = <&cpg>;
186 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
187 resets = <&cpg R9A07G043_RSPI1_RST>;
190 power-domains = <&cpg>;
204 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
205 resets = <&cpg R9A07G043_RSPI2_RST>;
208 power-domains = <&cpg>;
227 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
229 power-domains = <&cpg>;
230 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
246 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
248 power-domains = <&cpg>;
249 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>;
265 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
267 power-domains = <&cpg>;
268 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>;
284 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
286 power-domains = <&cpg>;
287 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>;
303 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
305 power-domains = <&cpg>;
306 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>;
318 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
320 power-domains = <&cpg>;
321 resets = <&cpg R9A07G043_SCI0_RST>;
333 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
335 power-domains = <&cpg>;
336 resets = <&cpg R9A07G043_SCI1_RST>;
354 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>,
355 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,
358 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;
360 resets = <&cpg R9A07G043_CANFD_RSTP_N>,
361 <&cpg R9A07G043_CANFD_RSTC_N>;
363 power-domains = <&cpg>;
389 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
391 resets = <&cpg R9A07G043_I2C0_MRST>;
392 power-domains = <&cpg>;
411 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
413 resets = <&cpg R9A07G043_I2C1_MRST>;
414 power-domains = <&cpg>;
433 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
435 resets = <&cpg R9A07G043_I2C2_MRST>;
436 power-domains = <&cpg>;
455 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
457 resets = <&cpg R9A07G043_I2C3_MRST>;
458 power-domains = <&cpg>;
466 clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
467 <&cpg CPG_MOD R9A07G043_ADC_PCLK>;
469 resets = <&cpg R9A07G043_ADC_PRESETN>,
470 <&cpg R9A07G043_ADC_ADRST_N>;
472 power-domains = <&cpg>;
490 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>;
491 resets = <&cpg R9A07G043_TSU_PRESETN>;
492 power-domains = <&cpg>;
503 clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
504 <&cpg CPG_MOD R9A07G043_SPI_CLK>;
505 resets = <&cpg R9A07G043_SPI_RST>;
506 power-domains = <&cpg>;
512 cpg: clock-controller@11010000 { label
513 compatible = "renesas,r9a07g043-cpg";
536 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
537 power-domains = <&cpg>;
538 resets = <&cpg R9A07G043_GPIO_RSTN>,
539 <&cpg R9A07G043_GPIO_PORT_RESETN>,
540 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
570 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
571 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
572 power-domains = <&cpg>;
573 resets = <&cpg R9A07G043_DMAC_ARESETN>,
574 <&cpg R9A07G043_DMAC_RST_ASYNC>;
585 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
586 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
587 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
588 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
590 resets = <&cpg R9A07G043_SDHI0_IXRST>;
591 power-domains = <&cpg>;
601 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
602 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
603 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
604 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
606 resets = <&cpg R9A07G043_SDHI1_IXRST>;
607 power-domains = <&cpg>;
620 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
621 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>,
622 <&cpg CPG_CORE R9A07G043_CLK_HP>;
624 resets = <&cpg R9A07G043_ETH0_RST_HW_N>;
625 power-domains = <&cpg>;
640 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
641 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>,
642 <&cpg CPG_CORE R9A07G043_CLK_HP>;
644 resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
645 power-domains = <&cpg>;
655 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>;
656 resets = <&cpg R9A07G043_USB_PRESETN>;
657 power-domains = <&cpg>;
666 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
667 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
669 <&cpg R9A07G043_USB_U2H0_HRESETN>;
672 power-domains = <&cpg>;
680 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
681 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
683 <&cpg R9A07G043_USB_U2H1_HRESETN>;
686 power-domains = <&cpg>;
694 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
695 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
697 <&cpg R9A07G043_USB_U2H0_HRESETN>;
701 power-domains = <&cpg>;
709 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
710 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
712 <&cpg R9A07G043_USB_U2H1_HRESETN>;
716 power-domains = <&cpg>;
725 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
726 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
729 power-domains = <&cpg>;
738 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
739 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
742 power-domains = <&cpg>;
754 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
755 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
757 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>;
761 power-domains = <&cpg>;
769 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
770 <&cpg CPG_MOD R9A07G043_WDT0_CLK>;
775 resets = <&cpg R9A07G043_WDT0_PRESETN>;
776 power-domains = <&cpg>;
785 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
786 resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
787 power-domains = <&cpg>;
796 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
797 resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
798 power-domains = <&cpg>;
807 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
808 resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
809 power-domains = <&cpg>;