Lines Matching refs:cpg
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
181 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
182 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
185 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
188 power-domains = <&cpg>;
202 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
203 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
206 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
209 power-domains = <&cpg>;
223 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
224 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
227 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
230 power-domains = <&cpg>;
244 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
245 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
248 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
251 power-domains = <&cpg>;
263 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
264 resets = <&cpg R9A07G054_RSPI0_RST>;
267 power-domains = <&cpg>;
281 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
282 resets = <&cpg R9A07G054_RSPI1_RST>;
285 power-domains = <&cpg>;
299 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
300 resets = <&cpg R9A07G054_RSPI2_RST>;
303 power-domains = <&cpg>;
322 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
324 power-domains = <&cpg>;
325 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
341 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
343 power-domains = <&cpg>;
344 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
360 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
362 power-domains = <&cpg>;
363 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
379 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
381 power-domains = <&cpg>;
382 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
398 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
400 power-domains = <&cpg>;
401 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
413 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
415 power-domains = <&cpg>;
416 resets = <&cpg R9A07G054_SCI0_RST>;
428 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
430 power-domains = <&cpg>;
431 resets = <&cpg R9A07G054_SCI1_RST>;
449 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
450 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
453 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
455 resets = <&cpg R9A07G054_CANFD_RSTP_N>,
456 <&cpg R9A07G054_CANFD_RSTC_N>;
458 power-domains = <&cpg>;
484 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
486 resets = <&cpg R9A07G054_I2C0_MRST>;
487 power-domains = <&cpg>;
506 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
508 resets = <&cpg R9A07G054_I2C1_MRST>;
509 power-domains = <&cpg>;
528 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
530 resets = <&cpg R9A07G054_I2C2_MRST>;
531 power-domains = <&cpg>;
550 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
552 resets = <&cpg R9A07G054_I2C3_MRST>;
553 power-domains = <&cpg>;
561 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
562 <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
564 resets = <&cpg R9A07G054_ADC_PRESETN>,
565 <&cpg R9A07G054_ADC_ADRST_N>;
567 power-domains = <&cpg>;
603 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
604 resets = <&cpg R9A07G054_TSU_PRESETN>;
605 power-domains = <&cpg>;
617 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
618 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
619 resets = <&cpg R9A07G054_SPI_RST>;
620 power-domains = <&cpg>;
626 cpg: clock-controller@11010000 { label
627 compatible = "renesas,r9a07g054-cpg";
658 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
659 power-domains = <&cpg>;
660 resets = <&cpg R9A07G054_GPIO_RSTN>,
661 <&cpg R9A07G054_GPIO_PORT_RESETN>,
662 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
713 clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
714 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
716 power-domains = <&cpg>;
717 resets = <&cpg R9A07G054_IA55_RESETN>;
747 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
748 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
749 power-domains = <&cpg>;
750 resets = <&cpg R9A07G054_DMAC_ARESETN>,
751 <&cpg R9A07G054_DMAC_RST_ASYNC>;
765 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
766 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
767 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
769 power-domains = <&cpg>;
770 resets = <&cpg R9A07G054_GPU_RESETN>,
771 <&cpg R9A07G054_GPU_AXI_RESETN>,
772 <&cpg R9A07G054_GPU_ACE_RESETN>;
793 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
794 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
795 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
796 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
798 resets = <&cpg R9A07G054_SDHI0_IXRST>;
799 power-domains = <&cpg>;
809 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
810 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
811 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
812 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
814 resets = <&cpg R9A07G054_SDHI1_IXRST>;
815 power-domains = <&cpg>;
828 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
829 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
830 <&cpg CPG_CORE R9A07G054_CLK_HP>;
832 resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
833 power-domains = <&cpg>;
848 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
849 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
850 <&cpg CPG_CORE R9A07G054_CLK_HP>;
852 resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
853 power-domains = <&cpg>;
863 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
864 resets = <&cpg R9A07G054_USB_PRESETN>;
865 power-domains = <&cpg>;
874 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
875 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
877 <&cpg R9A07G054_USB_U2H0_HRESETN>;
880 power-domains = <&cpg>;
888 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
889 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
891 <&cpg R9A07G054_USB_U2H1_HRESETN>;
894 power-domains = <&cpg>;
902 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
903 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
905 <&cpg R9A07G054_USB_U2H0_HRESETN>;
909 power-domains = <&cpg>;
917 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
918 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
920 <&cpg R9A07G054_USB_U2H1_HRESETN>;
924 power-domains = <&cpg>;
933 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
934 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
937 power-domains = <&cpg>;
946 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
947 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
950 power-domains = <&cpg>;
962 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
963 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
965 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
969 power-domains = <&cpg>;
977 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
978 <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
983 resets = <&cpg R9A07G054_WDT0_PRESETN>;
984 power-domains = <&cpg>;
992 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
993 <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
998 resets = <&cpg R9A07G054_WDT1_PRESETN>;
999 power-domains = <&cpg>;
1008 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
1009 resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
1010 power-domains = <&cpg>;
1019 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
1020 resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
1021 power-domains = <&cpg>;
1030 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
1031 resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
1032 power-domains = <&cpg>;