Lines Matching refs:Op1
300 switch (p->Op1) { in access_gic_sgi()
1669 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
2246 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
2248 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
2250 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
2252 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
2255 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
2264 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
2266 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
2270 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
2273 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
2275 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
2278 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
2280 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
2285 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
2287 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
2290 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
2302 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
2306 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
2309 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
2313 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
2316 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
2330 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
2333 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
2335 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
2337 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
2339 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
2341 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
2343 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
2349 { Op1( 0), CRm( 1), .access = trap_raz_wi },
2352 { Op1( 0), CRm( 2), .access = trap_raz_wi },
2357 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \
2377 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
2378 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
2380 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
2382 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
2383 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2384 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
2386 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
2388 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
2389 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
2391 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
2392 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
2394 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
2396 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
2398 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
2400 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
2405 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2406 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2407 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2431 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
2433 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
2435 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2437 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
2440 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2442 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
2515 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2516 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2519 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },
2521 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2525 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2527 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2528 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2529 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2530 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2658 params.Op1 = (esr >> 16) & 0xf; in kvm_handle_cp_64()
2704 params->Op1 = 0; in kvm_esr_cp10_id_to_sys64()
2848 if (params.Op1 == 0 && params.CRn == 0 && params.CRm) in kvm_handle_cp15_32()
2962 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) in index_to_params()
3235 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | in sys_reg_to_index()