Lines Matching refs:x3
34 mov x3, x1
35 dcache_by_line_op cvau, ish, x2, x3, x4, x5, \fixup
41 invalidate_icache_by_line x0, x1, x2, x3, \fixup
72 uaccess_ttbr0_enable x2, x3, x4
98 invalidate_icache_by_line x0, x1, x2, x3
112 dcache_by_line_op civac, sy, x0, x1, x2, x3
131 dcache_by_line_op cvau, ish, x0, x1, x2, x3
146 dcache_line_size x2, x3
147 sub x3, x2, #1
148 tst x1, x3 // end cache line aligned?
149 bic x1, x1, x3
152 1: tst x0, x3 // start cache line aligned?
153 bic x0, x0, x3
176 dcache_by_line_op cvac, sy, x0, x1, x2, x3
194 dcache_by_line_op cvap, sy, x0, x1, x2, x3