Lines Matching refs:r18
116 movl r18=PAGE_SHIFT
130 cmp.ne p8,p0=r18,r26
131 sub r27=r26,r18
133 (p8) dep r25=r18,r25,2,6
138 shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit
149 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
150 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
155 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
164 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
168 dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
170 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr)
179 (p7) ld8 r18=[r21] // read *pte
182 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
188 ITC_I_AND_D(p10, p11, r18, r24) // insert the instruction TLB entry and
240 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did *pte change
267 1: ld8 r18=[r17] // read *pte
270 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
273 ITC_I(p0, r18, r19)
285 cmp.ne p7,p0=r18,r19
311 1: ld8 r18=[r17] // read *pte
314 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
317 ITC_D(p0, r18, r19)
329 cmp.ne p7,p0=r18,r19
361 shr.u r18=r16,57 // move address bit 61 to bit 4
363 andcm r18=0x10,r18 // bit 4=~address-bit(61)
367 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
370 ITC_I(p0, r19, r18) // insert the TLB entry
425 ITC_D(p7, r19, r18) // insert the TLB entry
459 MOV_FROM_ITIR(r18)
462 extr.u r18=r18,2,6 // get the faulting page size
465 add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address
466 add r18=PGDIR_SHIFT-PAGE_SHIFT,r18
469 shr.u r18=r16,r18
479 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
480 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
483 shr.u r18=r22,PUD_SHIFT // shift pud index into position
485 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
491 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr)
495 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
498 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
544 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
550 1: ld8 r18=[r17]
552 mov ar.ccv=r18 // set compare value for cmpxchg
553 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
554 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
559 (p6) cmp.eq p6,p7=r26,r18 // Only compare if page is present
561 ITC_D(p6, r25, r18) // install updated PTE
569 ld8 r18=[r17] // read PTE again
571 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
578 1: ld8 r18=[r17]
580 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
583 st8 [r17]=r18 // store back updated PTE
584 ITC_D(p0, r18, r16) // install updated PTE
605 MOV_FROM_IIP(r18)
608 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
611 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
616 1: ld8 r18=[r17]
618 mov ar.ccv=r18 // set compare value for cmpxchg
619 or r25=_PAGE_A,r18 // set the accessed bit
620 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
625 (p6) cmp.eq p6,p7=r26,r18 // Only if page present
635 ld8 r18=[r17] // read PTE again
637 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
644 1: ld8 r18=[r17]
646 or r18=_PAGE_A,r18 // set the accessed bit
649 st8 [r17]=r18 // store back updated PTE
650 ITC_I(p0, r18, r16) // install updated PTE
665 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
671 1: ld8 r18=[r17]
673 mov ar.ccv=r18 // set compare value for cmpxchg
674 or r25=_PAGE_A,r18 // set the dirty bit
675 tbit.z p7,p6 = r18,_PAGE_P_BIT // Check present bit
680 (p6) cmp.eq p6,p7=r26,r18 // Only if page is present
689 ld8 r18=[r17] // read PTE again
691 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
697 1: ld8 r18=[r17]
699 or r18=_PAGE_A,r18 // set the accessed bit
701 st8 [r17]=r18 // store back updated PTE
702 ITC_D(p0, r18, r16) // install updated PTE
735 mov r18=__IA64_BREAK_SYSCALL // A
753 cmp.eq p0,p7=r18,r17 // I0 is this a system call?
808 MOV_FROM_ITC(p0, p14, r30, r18) // M get cycle for accounting
815 mov r18=ar.bsp // M2 (12 cyc)
829 ld8 r18=[r16],TI_AC_STIME-TI_AC_STAMP // M get last stamp
834 sub r22=r19,r18 // A stime before leave
837 sub r18=r30,r19 // A elapsed time in user
840 add r21=r21,r18 // A sum utime
957 (pKStk) mov r18=r0 // make sure r18 isn't NaT
979 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
993 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
999 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
1062 ld8 r18=[r16],TI_AC_STIME-TI_AC_STAMP // time at last check in kernel
1067 sub r22=r19,r18 // stime before leave kernel
1070 sub r18=r20,r19 // elapsed time in user mode
1073 add r21=r21,r18 // sum utime
1201 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1204 cmp.ne.or p6,p0=IA64_ISR_CODE_LFETCH,r18
1208 MOV_TO_IPSR(p0, r16, r18)
1233 MOV_FROM_IIM(r18)
1236 shl r18=r18,43 // put sign bit in position (43=64-21)
1240 shr r18=r18,39 // sign extend (39=43-4)
1243 add r17=r17,r18 // now add the offset