Lines Matching refs:imm
17 unsigned int imm = insn.reg1i20_format.immediate; in simu_pc() local
26 regs->regs[rd] = pc + sign_extend64(imm << 2, 21); in simu_pc()
29 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc()
32 regs->regs[rd] = pc + sign_extend64(imm << 18, 37); in simu_pc()
35 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc()
48 unsigned int imm, imm_l, imm_h, rd, rj; in simu_branch() local
86 imm = insn.reg2i16_format.immediate; in simu_branch()
92 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch()
98 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch()
104 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch()
110 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch()
116 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch()
122 regs->csr_era = pc + sign_extend64(imm << 2, 17); in simu_branch()
127 regs->csr_era = regs->regs[rj] + sign_extend64(imm << 2, 17); in simu_branch()
225 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm) in larch_insn_gen_lu12iw() argument
229 emit_lu12iw(&insn, rd, imm); in larch_insn_gen_lu12iw()
234 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm) in larch_insn_gen_lu32id() argument
238 emit_lu32id(&insn, rd, imm); in larch_insn_gen_lu32id()
243 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm) in larch_insn_gen_lu52id() argument
247 emit_lu52id(&insn, rd, rj, imm); in larch_insn_gen_lu52id()