Lines Matching refs:via1
41 volatile __u8 *via1, *via2; variable
113 via1 = (void *)VIA1_BASE; in via_init()
114 pr_debug("VIA1 detected at %p\n", via1); in via_init()
170 via1[vIER] = 0x7F; in via_init()
171 via1[vIFR] = 0x7F; in via_init()
172 via1[vT1CL] = 0; in via_init()
173 via1[vT1CH] = 0; in via_init()
174 via1[vT2CL] = 0; in via_init()
175 via1[vT2CH] = 0; in via_init()
176 via1[vACR] &= ~0xC0; /* setup T1 timer with no PB7 output */ in via_init()
177 via1[vACR] &= ~0x03; /* disable port A & B latches */ in via_init()
184 via1[vDirB] |= 0x40; in via_init()
185 via1[vBufB] |= 0x40; in via_init()
196 via1[vDirB] |= VIA1B_vRTCEnb | VIA1B_vRTCClk | VIA1B_vRTCData; in via_init()
197 via1[vBufB] |= VIA1B_vRTCEnb | VIA1B_vRTCClk; in via_init()
212 via1[vDirB] |= 0x40; in via_init()
213 via1[vBufB] &= ~0x40; in via_init()
268 (uint) via1[vDirA], (uint) via1[vDirB], (uint) via1[vACR]); in via_debug_dump()
270 (uint) via1[vPCR], (uint) via1[vIFR], (uint) via1[vIER]); in via_debug_dump()
387 events = via1[vIFR] & via1[vIER] & 0x7F; in via1_irq()
397 via1[vIFR] = irq_bit; in via1_irq()
410 via1[vIFR] = irq_bit; in via1_irq()
502 via1[vIER] = IER_SET_BIT(irq_idx); in via_irq_enable()
530 via1[vIER] = IER_CLR_BIT(irq_idx); in via_irq_disable()
551 via1[vBufA] &= ~VIA1A_vHeadSel; in via1_set_head()
553 via1[vBufA] |= VIA1A_vHeadSel; in via1_set_head()
601 via1[vT1CL] = VIA_TC_LOW; in via_init_clock()
602 via1[vT1CH] = VIA_TC_HIGH; in via_init_clock()
603 via1[vACR] |= 0x40; in via_init_clock()
625 count_high = via1[vT1CH]; in mac_read_clk()
628 if (count_high > 0 && (via1[vIFR] & VIA_TIMER_1_INT)) in mac_read_clk()