Lines Matching refs:T0
31 #define T0 8 macro
38 #define T0 12 macro
299 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, pc), K1); in kvm_mips_build_enter_guest()
300 UASM_i_MTC0(&p, T0, C0_EPC); in kvm_mips_build_enter_guest()
341 uasm_i_mfc0(&p, T0, C0_GUESTCTL1); in kvm_mips_build_enter_guest()
343 uasm_i_ext(&p, T1, T0, MIPS_GCTL1_ID_SHIFT, in kvm_mips_build_enter_guest()
345 uasm_i_ins(&p, T0, T1, MIPS_GCTL1_RID_SHIFT, in kvm_mips_build_enter_guest()
347 uasm_i_mtc0(&p, T0, C0_GUESTCTL1); in kvm_mips_build_enter_guest()
595 uasm_i_mfhi(&p, T0); in kvm_mips_build_exit()
596 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, hi), K1); in kvm_mips_build_exit()
598 uasm_i_mflo(&p, T0); in kvm_mips_build_exit()
599 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, lo), K1); in kvm_mips_build_exit()
604 UASM_i_MFC0(&p, T0, scratch_tmp[0], scratch_tmp[1]); in kvm_mips_build_exit()
605 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, gprs[K1]), K1); in kvm_mips_build_exit()
663 uasm_i_cfc1(&p, T0, 31); in kvm_mips_build_exit()
664 uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.fcr31), in kvm_mips_build_exit()
675 uasm_i_mfc0(&p, T0, C0_CONFIG5); in kvm_mips_build_exit()
676 uasm_i_ext(&p, T0, T0, 27, 1); /* MIPS_CONF5_MSAEN */ in kvm_mips_build_exit()
677 uasm_il_beqz(&p, &r, T0, label_msa_1); in kvm_mips_build_exit()
679 uasm_i_cfcmsa(&p, T0, MSA_CSR); in kvm_mips_build_exit()
680 uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.msacsr), in kvm_mips_build_exit()
723 uasm_i_mfc0(&p, T0, C0_GUESTCTL1); in kvm_mips_build_exit()
725 uasm_i_ins(&p, T0, ZERO, MIPS_GCTL1_RID_SHIFT, in kvm_mips_build_exit()
727 uasm_i_mtc0(&p, T0, C0_GUESTCTL1); in kvm_mips_build_exit()
818 uasm_i_andi(&p, T0, V0, RESUME_HOST); in kvm_mips_build_ret_from_exit()
819 uasm_il_bnez(&p, &r, T0, label_return_to_host); in kvm_mips_build_ret_from_exit()
849 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1); in kvm_mips_build_ret_to_guest()
857 build_set_exc_base(&p, T0); in kvm_mips_build_ret_to_guest()