Lines Matching refs:ori
38 l.ori gpr,gpr,lo(symbol)
265 l.ori r30,r30,(EXCEPTION_SR) ;\
351 l.ori r30,r0,(EXCEPTION_SR) ;\
525 l.ori r3,r0,0x1
583 l.ori r4,r0,0x0
624 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
650 l.ori r4,r4,lo(OF_DT_HEADER)
742 l.ori r25,r25,SPR_SR_IEE
747 l.ori r25,r25,0xffff
798 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
849 l.ori r30,r0,16
858 l.ori r30,r0,1
876 l.ori r6,r6,SPR_SR_ICE
915 l.ori r30,r0,16
924 l.ori r30,r0,1
938 l.ori r6,r6,SPR_SR_DCE
1010 l.ori r5, r0, 0x1
1016 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1018 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1030 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1032 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1097 l.ori r5, r0, 0x1
1103 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1105 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1123 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1125 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1210 l.ori r3, r0, 0x1
1222 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1295 l.ori r3, r0, 0x1
1310 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1317 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1356 l.ori r4,r4,lo(UART_BASE_ADD)
1509 l.ori r3,r3,lo(UART_BASE_ADD)
1522 l.ori r4,r5,0x80
1540 l.ori r3,r0,SPR_SR_SM