Lines Matching defs:fsl_lbc_regs
90 struct fsl_lbc_regs { struct
91 struct fsl_lbc_bank bank[12];
92 u8 res0[0x8];
93 __be32 mar; /**< UPM Address Register */
94 u8 res1[0x4];
95 __be32 mamr; /**< UPMA Mode Register */
101 __be32 mbmr; /**< UPMB Mode Register */
102 __be32 mcmr; /**< UPMC Mode Register */
103 u8 res2[0x8];
104 __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
105 __be32 mdr; /**< UPM Data Register */
106 u8 res3[0x4];
107 __be32 lsor; /**< Special Operation Initiation Register */
108 __be32 lsdmr; /**< SDRAM Mode Register */
109 u8 res4[0x8];
110 __be32 lurt; /**< UPM Refresh Timer */
111 __be32 lsrt; /**< SDRAM Refresh Timer */
112 u8 res5[0x8];
113 __be32 ltesr; /**< Transfer Error Status Register */
132 __be32 ltedr; /**< Transfer Error Disable Register */
133 __be32 lteir; /**< Transfer Error Interrupt Register */
134 __be32 lteatr; /**< Transfer Error Attributes Register */
135 __be32 ltear; /**< Transfer Error Address Register */
136 __be32 lteccr; /**< Transfer Error ECC Register */
137 u8 res6[0x8];
138 __be32 lbcr; /**< Configuration Register */
153 __be32 lcrr; /**< Clock Ratio Register */
164 u8 res7[0x8];
165 __be32 fmr; /**< Flash Mode Register */
174 __be32 fir; /**< Flash Instruction Register */
207 __be32 fcr; /**< Flash Command Register */
216 __be32 fbar; /**< Flash Block Address Register */
218 __be32 fpar; /**< Flash Page Address Register */
229 __be32 fbcr; /**< Flash Byte Count Register */