Lines Matching refs:spu
26 struct spu *spu = ctx->spu; in spu_hw_mbox_read() local
27 struct spu_problem __iomem *prob = spu->problem; in spu_hw_mbox_read()
31 spin_lock_irq(&spu->register_lock); in spu_hw_mbox_read()
37 spin_unlock_irq(&spu->register_lock); in spu_hw_mbox_read()
43 return in_be32(&ctx->spu->problem->mb_stat_R); in spu_hw_mbox_stat_read()
48 struct spu *spu = ctx->spu; in spu_hw_mbox_stat_poll() local
52 spin_lock_irq(&spu->register_lock); in spu_hw_mbox_stat_poll()
53 stat = in_be32(&spu->problem->mb_stat_R); in spu_hw_mbox_stat_poll()
64 spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR); in spu_hw_mbox_stat_poll()
65 spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR); in spu_hw_mbox_stat_poll()
72 spu_int_stat_clear(spu, 2, in spu_hw_mbox_stat_poll()
74 spu_int_mask_or(spu, 2, in spu_hw_mbox_stat_poll()
78 spin_unlock_irq(&spu->register_lock); in spu_hw_mbox_stat_poll()
84 struct spu *spu = ctx->spu; in spu_hw_ibox_read() local
85 struct spu_problem __iomem *prob = spu->problem; in spu_hw_ibox_read()
86 struct spu_priv2 __iomem *priv2 = spu->priv2; in spu_hw_ibox_read()
89 spin_lock_irq(&spu->register_lock); in spu_hw_ibox_read()
96 spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR); in spu_hw_ibox_read()
99 spin_unlock_irq(&spu->register_lock); in spu_hw_ibox_read()
105 struct spu *spu = ctx->spu; in spu_hw_wbox_write() local
106 struct spu_problem __iomem *prob = spu->problem; in spu_hw_wbox_write()
109 spin_lock_irq(&spu->register_lock); in spu_hw_wbox_write()
117 spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR); in spu_hw_wbox_write()
120 spin_unlock_irq(&spu->register_lock); in spu_hw_wbox_write()
126 out_be32(&ctx->spu->problem->signal_notify1, data); in spu_hw_signal1_write()
131 out_be32(&ctx->spu->problem->signal_notify2, data); in spu_hw_signal2_write()
136 struct spu *spu = ctx->spu; in spu_hw_signal1_type_set() local
137 struct spu_priv2 __iomem *priv2 = spu->priv2; in spu_hw_signal1_type_set()
140 spin_lock_irq(&spu->register_lock); in spu_hw_signal1_type_set()
147 spin_unlock_irq(&spu->register_lock); in spu_hw_signal1_type_set()
152 return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0); in spu_hw_signal1_type_get()
157 struct spu *spu = ctx->spu; in spu_hw_signal2_type_set() local
158 struct spu_priv2 __iomem *priv2 = spu->priv2; in spu_hw_signal2_type_set()
161 spin_lock_irq(&spu->register_lock); in spu_hw_signal2_type_set()
168 spin_unlock_irq(&spu->register_lock); in spu_hw_signal2_type_set()
173 return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0); in spu_hw_signal2_type_get()
178 return in_be32(&ctx->spu->problem->spu_npc_RW); in spu_hw_npc_read()
183 out_be32(&ctx->spu->problem->spu_npc_RW, val); in spu_hw_npc_write()
188 return in_be32(&ctx->spu->problem->spu_status_R); in spu_hw_status_read()
193 return ctx->spu->local_store; in spu_hw_get_ls()
198 out_be64(&ctx->spu->priv2->spu_privcntl_RW, val); in spu_hw_privcntl_write()
203 return in_be32(&ctx->spu->problem->spu_runcntl_RW); in spu_hw_runcntl_read()
208 spin_lock_irq(&ctx->spu->register_lock); in spu_hw_runcntl_write()
212 out_be32(&ctx->spu->problem->spu_runcntl_RW, val); in spu_hw_runcntl_write()
213 spin_unlock_irq(&ctx->spu->register_lock); in spu_hw_runcntl_write()
218 spin_lock_irq(&ctx->spu->register_lock); in spu_hw_runcntl_stop()
219 out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP); in spu_hw_runcntl_stop()
220 while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING) in spu_hw_runcntl_stop()
222 spin_unlock_irq(&ctx->spu->register_lock); in spu_hw_runcntl_stop()
227 struct spu *spu = ctx->spu; in spu_hw_master_start() local
230 spin_lock_irq(&spu->register_lock); in spu_hw_master_start()
231 sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_hw_master_start()
232 spu_mfc_sr1_set(spu, sr1); in spu_hw_master_start()
233 spin_unlock_irq(&spu->register_lock); in spu_hw_master_start()
238 struct spu *spu = ctx->spu; in spu_hw_master_stop() local
241 spin_lock_irq(&spu->register_lock); in spu_hw_master_stop()
242 sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_hw_master_stop()
243 spu_mfc_sr1_set(spu, sr1); in spu_hw_master_stop()
244 spin_unlock_irq(&spu->register_lock); in spu_hw_master_stop()
249 struct spu_problem __iomem *prob = ctx->spu->problem; in spu_hw_set_mfc_query()
252 spin_lock_irq(&ctx->spu->register_lock); in spu_hw_set_mfc_query()
260 spin_unlock_irq(&ctx->spu->register_lock); in spu_hw_set_mfc_query()
266 return in_be32(&ctx->spu->problem->dma_tagstatus_R); in spu_hw_read_mfc_tagstatus()
271 return in_be32(&ctx->spu->problem->dma_qstatus_R); in spu_hw_get_mfc_free_elements()
278 struct spu_problem __iomem *prob = ctx->spu->problem; in spu_hw_send_mfc_command()
280 spin_lock_irq(&ctx->spu->register_lock); in spu_hw_send_mfc_command()
288 spin_unlock_irq(&ctx->spu->register_lock); in spu_hw_send_mfc_command()
302 struct spu_priv2 __iomem *priv2 = ctx->spu->priv2; in spu_hw_restart_dma()
304 if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &ctx->spu->flags)) in spu_hw_restart_dma()