Lines Matching refs:eeh_ops

76 	if (!eeh_ops || !eeh_ops->err_inject)  in pnv_eeh_ei_write()
96 	ret = eeh_ops->err_inject(pe, type, func, addr, mask);  in pnv_eeh_ei_write()
818 			eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,  in __pnv_eeh_bridge_reset()
821 			eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,  in __pnv_eeh_bridge_reset()
825 		eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);  in __pnv_eeh_bridge_reset()
827 		eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);  in __pnv_eeh_bridge_reset()
832 		eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);  in __pnv_eeh_bridge_reset()
834 		eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl);  in __pnv_eeh_bridge_reset()
840 			eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,  in __pnv_eeh_bridge_reset()
843 			eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK,  in __pnv_eeh_bridge_reset()
917 		eeh_ops->read_config(edev, pos, 2, &status);  in pnv_eeh_wait_for_pending()
938 	eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, &reg);  in pnv_eeh_do_flr()
948 		eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,  in pnv_eeh_do_flr()
951 		eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,  in pnv_eeh_do_flr()
956 		eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,  in pnv_eeh_do_flr()
959 		eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,  in pnv_eeh_do_flr()
976 	eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap);  in pnv_eeh_do_af_flr()
991 		eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL,  in pnv_eeh_do_af_flr()
996 		eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0);  in pnv_eeh_do_af_flr()
1379 		ret = eeh_ops->get_state(dev_pe, NULL);  in pnv_eeh_get_pe()
1575 				state = eeh_ops->get_state(parent_pe, NULL);  in pnv_eeh_next_error()
1628 static struct eeh_ops pnv_eeh_ops = {