Lines Matching refs:psw

31 	if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT)  in arch_uprobe_pre_xol()
33 	if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT)  in arch_uprobe_pre_xol()
36 	auprobe->saved_per = psw_bits(regs->psw).per;  in arch_uprobe_pre_xol()
39 	regs->psw.addr = current->utask->xol_vaddr;  in arch_uprobe_pre_xol()
57 	if (!(regs->psw.mask & PSW_MASK_PER))  in check_per_event()
71 		    regs->psw.addr >= current->thread.per_user.start &&  in check_per_event()
72 		    regs->psw.addr <= current->thread.per_user.end)  in check_per_event()
85 	psw_bits(regs->psw).per = auprobe->saved_per;  in arch_uprobe_post_xol()
89 		regs->psw.addr += utask->vaddr - utask->xol_vaddr;  in arch_uprobe_post_xol()
98 		if (regs->psw.addr - utask->xol_vaddr == ilen)  in arch_uprobe_post_xol()
99 			regs->psw.addr = utask->vaddr + ilen;  in arch_uprobe_post_xol()
140 	regs->psw.addr = current->utask->vaddr;  in arch_uprobe_abort_xol()
165 static void adjust_psw_addr(psw_t *psw, unsigned long len)  in adjust_psw_addr()  argument
167 	psw->addr = __rewind_psw(*psw, -len);  in adjust_psw_addr()
217 		psw_bits((regs)->psw).cc = 1;		\
219 		psw_bits((regs)->psw).cc = 2;		\
221 		psw_bits((regs)->psw).cc = 0;		\
247 	if (!(regs->psw.mask & PSW_MASK_PER))  in sim_stor_event()
255 	current->thread.per_event.address = regs->psw.addr;  in sim_stor_event()
274 	uptr = (void *)(regs->psw.addr + (insn->disp * 2));  in handle_insn_ril()
357 	adjust_psw_addr(&regs->psw, ilen);  in handle_insn_ril()
376 	if ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) ||  in arch_uprobe_skip_sstep()
377 	    ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) &&  in arch_uprobe_skip_sstep()
379 		regs->psw.addr = __rewind_psw(regs->psw, UPROBE_SWBP_INSN_SIZE);  in arch_uprobe_skip_sstep()