Lines Matching refs:pbm
30 static int pci_fire_pbm_iommu_init(struct pci_pbm_info *pbm) in pci_fire_pbm_iommu_init() argument
32 struct iommu *iommu = pbm->iommu; in pci_fire_pbm_iommu_init()
44 iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL; in pci_fire_pbm_iommu_init()
45 iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE; in pci_fire_pbm_iommu_init()
46 iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH; in pci_fire_pbm_iommu_init()
47 iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV; in pci_fire_pbm_iommu_init()
52 iommu->write_complete_reg = pbm->controller_regs + 0x410000UL; in pci_fire_pbm_iommu_init()
60 pbm->numa_node); in pci_fire_pbm_iommu_init()
150 static int pci_fire_get_head(struct pci_pbm_info *pbm, unsigned long msiqid, in pci_fire_get_head() argument
153 *head = upa_readq(pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid)); in pci_fire_get_head()
157 static int pci_fire_dequeue_msi(struct pci_pbm_info *pbm, unsigned long msiqid, in pci_fire_dequeue_msi() argument
163 base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) * 8192)); in pci_fire_dequeue_msi()
179 upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num)); in pci_fire_dequeue_msi()
186 if (*head >= pbm->msiq_ent_count) in pci_fire_dequeue_msi()
192 static int pci_fire_set_head(struct pci_pbm_info *pbm, unsigned long msiqid, in pci_fire_set_head() argument
195 upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid)); in pci_fire_set_head()
199 static int pci_fire_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid, in pci_fire_msi_setup() argument
204 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_setup()
207 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_setup()
209 upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi)); in pci_fire_msi_setup()
211 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_setup()
213 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_setup()
218 static int pci_fire_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi) in pci_fire_msi_teardown() argument
222 val = upa_readq(pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_teardown()
226 upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi)); in pci_fire_msi_teardown()
231 static int pci_fire_msiq_alloc(struct pci_pbm_info *pbm) in pci_fire_msiq_alloc() argument
243 pbm->msi_queues = (void *) pages; in pci_fire_msiq_alloc()
246 __pa(pbm->msi_queues)), in pci_fire_msiq_alloc()
247 pbm->pbm_regs + EVENT_QUEUE_BASE_ADDR_REG); in pci_fire_msiq_alloc()
249 upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0); in pci_fire_msiq_alloc()
250 upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1); in pci_fire_msiq_alloc()
252 upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR); in pci_fire_msiq_alloc()
253 upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR); in pci_fire_msiq_alloc()
255 for (i = 0; i < pbm->msiq_num; i++) { in pci_fire_msiq_alloc()
256 upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i)); in pci_fire_msiq_alloc()
257 upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i)); in pci_fire_msiq_alloc()
263 static void pci_fire_msiq_free(struct pci_pbm_info *pbm) in pci_fire_msiq_free() argument
268 pages = (unsigned long) pbm->msi_queues; in pci_fire_msiq_free()
272 pbm->msi_queues = NULL; in pci_fire_msiq_free()
275 static int pci_fire_msiq_build_irq(struct pci_pbm_info *pbm, in pci_fire_msiq_build_irq() argument
279 unsigned long cregs = (unsigned long) pbm->pbm_regs; in pci_fire_msiq_build_irq()
295 fixup = ((pbm->portid << 6) | devino) - int_ctrlr; in pci_fire_msiq_build_irq()
302 pbm->pbm_regs + EVENT_QUEUE_CONTROL_SET(msiqid)); in pci_fire_msiq_build_irq()
318 static void pci_fire_msi_init(struct pci_pbm_info *pbm) in pci_fire_msi_init() argument
320 sparc64_pbm_msi_init(pbm, &pci_fire_msiq_ops); in pci_fire_msi_init()
323 static void pci_fire_msi_init(struct pci_pbm_info *pbm) in pci_fire_msi_init() argument
366 static void pci_fire_hw_init(struct pci_pbm_info *pbm) in pci_fire_hw_init() argument
371 pbm->controller_regs + FIRE_PARITY_CONTROL); in pci_fire_hw_init()
381 pbm->controller_regs + FIRE_FATAL_RESET_CTL); in pci_fire_hw_init()
383 upa_writeq(~(u64)0, pbm->controller_regs + FIRE_CORE_INTR_ENABLE); in pci_fire_hw_init()
385 val = upa_readq(pbm->pbm_regs + FIRE_TLU_CTRL); in pci_fire_hw_init()
389 upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL); in pci_fire_hw_init()
390 upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL); in pci_fire_hw_init()
392 pbm->pbm_regs + FIRE_TLU_LINK_CTRL); in pci_fire_hw_init()
394 upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET); in pci_fire_hw_init()
395 upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG); in pci_fire_hw_init()
397 pbm->pbm_regs + FIRE_LPU_FCTRL_UCTRL); in pci_fire_hw_init()
399 pbm->pbm_regs + FIRE_LPU_TXL_FIFOP); in pci_fire_hw_init()
400 upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2); in pci_fire_hw_init()
401 upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3); in pci_fire_hw_init()
403 pbm->pbm_regs + FIRE_LPU_LTSSM_CFG4); in pci_fire_hw_init()
404 upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5); in pci_fire_hw_init()
406 upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB); in pci_fire_hw_init()
407 upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A); in pci_fire_hw_init()
408 upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B); in pci_fire_hw_init()
410 upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB); in pci_fire_hw_init()
413 static int pci_fire_pbm_init(struct pci_pbm_info *pbm, in pci_fire_pbm_init() argument
420 pbm->numa_node = NUMA_NO_NODE; in pci_fire_pbm_init()
422 pbm->pci_ops = &sun4u_pci_ops; in pci_fire_pbm_init()
423 pbm->config_space_reg_bits = 12; in pci_fire_pbm_init()
425 pbm->index = pci_num_pbms++; in pci_fire_pbm_init()
427 pbm->portid = portid; in pci_fire_pbm_init()
428 pbm->op = op; in pci_fire_pbm_init()
429 pbm->name = dp->full_name; in pci_fire_pbm_init()
432 pbm->pbm_regs = regs[0].phys_addr; in pci_fire_pbm_init()
433 pbm->controller_regs = regs[1].phys_addr - 0x410000UL; in pci_fire_pbm_init()
435 printk("%s: SUN4U PCIE Bus Module\n", pbm->name); in pci_fire_pbm_init()
437 pci_determine_mem_io_space(pbm); in pci_fire_pbm_init()
439 pci_get_pbm_props(pbm); in pci_fire_pbm_init()
441 pci_fire_hw_init(pbm); in pci_fire_pbm_init()
443 err = pci_fire_pbm_iommu_init(pbm); in pci_fire_pbm_init()
447 pci_fire_msi_init(pbm); in pci_fire_pbm_init()
449 pbm->pci_bus = pci_scan_one_pbm(pbm, &op->dev); in pci_fire_pbm_init()
453 pbm->next = pci_pbm_root; in pci_fire_pbm_init()
454 pci_pbm_root = pbm; in pci_fire_pbm_init()
462 struct pci_pbm_info *pbm; in fire_probe() local
470 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL); in fire_probe()
471 if (!pbm) { in fire_probe()
482 pbm->iommu = iommu; in fire_probe()
484 err = pci_fire_pbm_init(pbm, op, portid); in fire_probe()
488 dev_set_drvdata(&op->dev, pbm); in fire_probe()
493 kfree(pbm->iommu); in fire_probe()
496 kfree(pbm); in fire_probe()