Lines Matching refs:round
181 #define R(i, a, b, c, d, e, f, g, h, round, widx, wtype) \ argument
185 leal K##round(t0, e, 1), t1; \
188 addl wtype##_W1_ADDR(round, widx), h; \
194 addl wtype##_W1W2_ADDR(round, widx), d; \
215 #define R1(a, b, c, d, e, f, g, h, round, widx, wtype) \ argument
216 R(1, a, b, c, d, e, f, g, h, round, widx, wtype)
218 #define R2(a, b, c, d, e, f, g, h, round, widx, wtype) \ argument
219 R(2, a, b, c, d, e, f, g, h, round, widx, wtype)
224 #define IW_W_ADDR(round, widx, offs) \ argument
225 (STACK_W + ((round) / 4) * 64 + (offs) + ((widx) * 4))(%rsp)
228 #define XW_W_ADDR(round, widx, offs) \ argument
229 (STACK_W + ((((round) / 3) - 4) % 2) * 64 + (offs) + ((widx) * 4))(%rsp)
232 #define IW_W1_ADDR(round, widx) IW_W_ADDR(round, widx, 0) argument
233 #define IW_W1W2_ADDR(round, widx) IW_W_ADDR(round, widx, 32) argument
236 #define XW_W1_ADDR(round, widx) XW_W_ADDR(round, widx, 0) argument
237 #define XW_W1W2_ADDR(round, widx) XW_W_ADDR(round, widx, 32) argument
271 #define SCHED_W_0(round, w0, w1, w2, w3, w4, w5) \ argument
282 #define SCHED_W_1(round, w0, w1, w2, w3, w4, w5) \ argument
307 #define SCHED_W_2(round, w0, w1, w2, w3, w4, w5) \ argument
311 vmovdqa XTMP4, XW_W1_ADDR((round), 0); \
314 vmovdqa XTMP1, XW_W1W2_ADDR((round), 0);