Lines Matching refs:x86_pmu
138 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source; in intel_pmu_pebs_data_source_adl()
142 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; in intel_pmu_pebs_data_source_adl()
161 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source; in intel_pmu_pebs_data_source_mtl()
165 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source; in intel_pmu_pebs_data_source_mtl()
312 if (x86_pmu.pebs_no_tlb) { in load_latency_data()
322 if (!x86_pmu.pebs_block) { in load_latency_data()
508 size_t bsiz = x86_pmu.pebs_buffer_size; in alloc_pebs_buffer()
512 if (!x86_pmu.pebs) in alloc_pebs_buffer()
523 if (x86_pmu.intel_cap.pebs_format < 2) { in alloc_pebs_buffer()
537 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size); in alloc_pebs_buffer()
547 if (!x86_pmu.pebs) in release_pebs_buffer()
555 ds_clear_cea(cea, x86_pmu.pebs_buffer_size); in release_pebs_buffer()
556 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); in release_pebs_buffer()
567 if (!x86_pmu.bts) in alloc_bts_buffer()
594 if (!x86_pmu.bts) in release_bts_buffer()
622 if (!x86_pmu.bts && !x86_pmu.pebs) in release_ds_buffers()
648 x86_pmu.bts_active = 0; in reserve_ds_buffers()
649 x86_pmu.pebs_active = 0; in reserve_ds_buffers()
651 if (!x86_pmu.bts && !x86_pmu.pebs) in reserve_ds_buffers()
654 if (!x86_pmu.bts) in reserve_ds_buffers()
657 if (!x86_pmu.pebs) in reserve_ds_buffers()
690 if (x86_pmu.bts && !bts_err) in reserve_ds_buffers()
691 x86_pmu.bts_active = 1; in reserve_ds_buffers()
693 if (x86_pmu.pebs && !pebs_err) in reserve_ds_buffers()
694 x86_pmu.pebs_active = 1; in reserve_ds_buffers()
770 if (!x86_pmu.bts_active) in intel_pmu_drain_bts_buffer()
845 x86_pmu.drain_pebs(NULL, &data); in intel_pmu_drain_pebs_buffer()
1104 if (x86_pmu.flags & PMU_FL_PEBS_ALL) in intel_pebs_constraints()
1142 if (x86_pmu.flags & PMU_FL_PEBS_ALL) in pebs_update_threshold()
1170 sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry); in adaptive_pebs_record_size_update()
1206 x86_pmu.rtm_abort_event); in pebs_update_adaptive_cfg()
1221 ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT); in pebs_update_adaptive_cfg()
1252 if (x86_pmu.intel_cap.pebs_baseline && add) { in pebs_update_state()
1321 if (x86_pmu.intel_cap.pebs_format < 5) in intel_pmu_pebs_via_pt_enable()
1340 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5)) in intel_pmu_pebs_enable()
1345 if (x86_pmu.intel_cap.pebs_baseline) { in intel_pmu_pebs_enable()
1354 if (x86_pmu.intel_cap.pebs_format < 5) in intel_pmu_pebs_enable()
1366 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; in intel_pmu_pebs_enable()
1401 (x86_pmu.version < 5)) in intel_pmu_pebs_disable()
1443 if (!x86_pmu.intel_cap.pebs_trap) in intel_pmu_pebs_fixup_ip()
1544 if (x86_pmu.intel_cap.pebs_format < 4) in get_pebs_status()
1565 val = x86_pmu.pebs_latency_data(event, aux); in get_data_src()
1692 if (x86_pmu.intel_cap.pebs_format >= 2) { in setup_pebs_fixed_sample_data()
1717 x86_pmu.intel_cap.pebs_format >= 1) { in setup_pebs_fixed_sample_data()
1722 if (x86_pmu.intel_cap.pebs_format >= 2) { in setup_pebs_fixed_sample_data()
1741 if (x86_pmu.intel_cap.pebs_format >= 3) in setup_pebs_fixed_sample_data()
1820 if ((sample_type & PERF_SAMPLE_WEIGHT_STRUCT) && (x86_pmu.flags & PMU_FL_RETIRE_LATENCY)) in setup_pebs_adaptive_sample_data()
1850 if (x86_pmu.flags & PMU_FL_INSTR_LATENCY) { in setup_pebs_adaptive_sample_data()
1924 if (x86_pmu.intel_cap.pebs_format < 1) in get_next_pebs_record_by_bit()
1935 if (x86_pmu.intel_cap.pebs_format >= 3) in get_next_pebs_record_by_bit()
1967 int shift = 64 - x86_pmu.cntval_bits; in intel_pmu_save_and_restart_reload()
2089 if (!x86_pmu.pebs_active) in intel_pmu_drain_pebs_core()
2149 if (!x86_pmu.pebs_active) in intel_pmu_drain_pebs_nhm()
2157 mask = (1ULL << x86_pmu.max_pebs_events) - 1; in intel_pmu_drain_pebs_nhm()
2158 size = x86_pmu.max_pebs_events; in intel_pmu_drain_pebs_nhm()
2159 if (x86_pmu.flags & PMU_FL_PEBS_ALL) { in intel_pmu_drain_pebs_nhm()
2160 mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED; in intel_pmu_drain_pebs_nhm()
2161 size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed; in intel_pmu_drain_pebs_nhm()
2169 for (at = base; at < top; at += x86_pmu.pebs_record_size) { in intel_pmu_drain_pebs_nhm()
2177 if (x86_pmu.intel_cap.pebs_format >= 3) { in intel_pmu_drain_pebs_nhm()
2197 x86_pmu.max_pebs_events); in intel_pmu_drain_pebs_nhm()
2198 if (bit >= x86_pmu.max_pebs_events) in intel_pmu_drain_pebs_nhm()
2264 if (!x86_pmu.pebs_active) in intel_pmu_drain_pebs_icl()
2320 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); in intel_ds_init()
2321 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); in intel_ds_init()
2322 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE; in intel_ds_init()
2323 if (x86_pmu.version <= 4) in intel_ds_init()
2324 x86_pmu.pebs_no_isolation = 1; in intel_ds_init()
2326 if (x86_pmu.pebs) { in intel_ds_init()
2327 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; in intel_ds_init()
2329 int format = x86_pmu.intel_cap.pebs_format; in intel_ds_init()
2332 x86_pmu.intel_cap.pebs_baseline = 0; in intel_ds_init()
2337 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); in intel_ds_init()
2345 x86_pmu.pebs_buffer_size = PAGE_SIZE; in intel_ds_init()
2346 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; in intel_ds_init()
2351 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm); in intel_ds_init()
2352 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; in intel_ds_init()
2357 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw); in intel_ds_init()
2358 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; in intel_ds_init()
2363 x86_pmu.pebs_record_size = in intel_ds_init()
2365 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; in intel_ds_init()
2366 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; in intel_ds_init()
2370 x86_pmu.pebs_ept = 1; in intel_ds_init()
2373 x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl; in intel_ds_init()
2374 x86_pmu.pebs_record_size = sizeof(struct pebs_basic); in intel_ds_init()
2375 if (x86_pmu.intel_cap.pebs_baseline) { in intel_ds_init()
2376 x86_pmu.large_pebs_flags |= in intel_ds_init()
2379 x86_pmu.flags |= PMU_FL_PEBS_ALL; in intel_ds_init()
2380 x86_pmu.pebs_capable = ~0ULL; in intel_ds_init()
2385 x86_pmu.large_pebs_flags &= in intel_ds_init()
2395 if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) { in intel_ds_init()
2404 x86_pmu.pebs = 0; in intel_ds_init()
2413 if (!x86_pmu.bts && !x86_pmu.pebs) in perf_restore_debug_store()