Lines Matching defs:cpu_hw_events
231 struct cpu_hw_events { struct
235 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
236 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
237 unsigned long dirty[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
238 int enabled;
240 int n_events; /* the # of events in the below arrays */
241 int n_added; /* the # last events in the below arrays;
243 int n_txn; /* the # last events in the below arrays;
245 int n_txn_pair;
246 int n_txn_metric;
247 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
248 u64 tags[X86_PMC_IDX_MAX];
250 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
251 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
253 int n_excl; /* the number of exclusive events */
255 unsigned int txn_flags;
256 int is_fake;
261 struct debug_store *ds;
262 void *ds_pebs_vaddr;
263 void *ds_bts_vaddr;
264 u64 pebs_enabled;
265 int n_pebs;
266 int n_large_pebs;
267 int n_pebs_via_pt;
268 int pebs_output;
271 u64 pebs_data_cfg;
272 u64 active_pebs_data_cfg;
273 int pebs_record_size;
276 u64 fixed_ctrl_val;
277 u64 active_fixed_ctrl_val;
282 int lbr_users;
283 int lbr_pebs_users;
284 struct perf_branch_stack lbr_stack;
285 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
286 union {
290 u64 br_sel;
291 void *last_task_ctx;
292 int last_log_id;
293 int lbr_select;
294 void *lbr_xsave;
299 u64 intel_ctrl_guest_mask;
300 u64 intel_ctrl_host_mask;
301 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
306 u64 intel_cp_status;
312 struct intel_shared_regs *shared_regs;
316 struct event_constraint *constraint_list; /* in enable order */
317 struct intel_excl_cntrs *excl_cntrs;
318 int excl_thread_id; /* 0 or 1 */
323 u64 tfa_shadow;
329 int n_metric;
334 struct amd_nb *amd_nb;
335 int brs_active; /* BRS is enabled */
338 u64 perf_ctr_virt_mask;
339 int n_pair; /* Large increment events */
341 void *kfree_on_online[X86_PERF_KFREE_MAX];
343 struct pmu *pmu;