Lines Matching refs:x86_pmu
696 typeof(&x86_pmu._field) __Fp = &x86_pmu._field; \
716 bool __Fp = x86_pmu._field; \
739 struct x86_pmu { struct
991 __quirk.next = x86_pmu.quirks; \
992 x86_pmu.quirks = &__quirk; \
1051 extern struct x86_pmu x86_pmu __read_mostly;
1053 DECLARE_STATIC_CALL(x86_pmu_set_period, *x86_pmu.set_period);
1054 DECLARE_STATIC_CALL(x86_pmu_update, *x86_pmu.update);
1066 return x86_pmu.lbr_sel_map && in x86_pmu_has_lbr_callstack()
1067 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0; in x86_pmu_has_lbr_callstack()
1098 return x86_pmu.eventsel + (x86_pmu.addr_offset ? in x86_pmu_config_addr()
1099 x86_pmu.addr_offset(index, true) : index); in x86_pmu_config_addr()
1104 return x86_pmu.perfctr + (x86_pmu.addr_offset ? in x86_pmu_event_addr()
1105 x86_pmu.addr_offset(index, false) : index); in x86_pmu_event_addr()
1110 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; in x86_pmu_rdpmc_index()
1157 wrmsrl(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); in __x86_pmu_enable_event()
1429 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); in intel_pmu_has_bts_period()
1627 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED); in is_ht_workaround_enabled()