Lines Matching refs:IA32_ECX
99 #define IA32_ECX (0x1) macro
290 u8 sreg = sstk ? IA32_ECX : src; in emit_ia32_mul_r()
294 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src)); in emit_ia32_mul_r()
412 EMIT2(0x89, add_2reg(0xC0, IA32_ECX, dreg_hi)); in emit_ia32_to_be_r64()
416 EMIT2(0x89, add_2reg(0xC0, dreg_lo, IA32_ECX)); in emit_ia32_to_be_r64()
443 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), in emit_ia32_div_mod_r()
445 else if (src != IA32_ECX) in emit_ia32_div_mod_r()
447 EMIT2(0x8B, add_2reg(0xC0, src, IA32_ECX)); in emit_ia32_div_mod_r()
460 EMIT2(0xF7, add_1reg(0xF0, IA32_ECX)); in emit_ia32_div_mod_r()
496 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src)); in emit_ia32_shift_r()
497 else if (src != IA32_ECX) in emit_ia32_shift_r()
499 EMIT2(0x8B, add_2reg(0xC0, src, IA32_ECX)); in emit_ia32_shift_r()
748 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), in emit_ia32_lsh_r64()
752 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX)); in emit_ia32_lsh_r64()
762 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32); in emit_ia32_lsh_r64()
801 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), in emit_ia32_arsh_r64()
805 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX)); in emit_ia32_arsh_r64()
815 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32); in emit_ia32_arsh_r64()
854 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), in emit_ia32_rsh_r64()
858 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX)); in emit_ia32_rsh_r64()
868 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32); in emit_ia32_rsh_r64()
1057 EMIT2(0x89, add_2reg(0xC0, IA32_ECX, IA32_EAX)); in emit_ia32_mul_r64()
1075 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EAX)); in emit_ia32_mul_r64()
1093 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX)); in emit_ia32_mul_r64()
1100 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX), in emit_ia32_mul_r64()
1106 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX)); in emit_ia32_mul_r64()
1130 EMIT2(0x89, add_2reg(0xC0, IA32_ECX, IA32_EAX)); in emit_ia32_mul_i64()
1141 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EAX)); in emit_ia32_mul_i64()
1153 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX)); in emit_ia32_mul_i64()
1160 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX), in emit_ia32_mul_i64()
1166 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX)); in emit_ia32_mul_i64()
1331 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0])); in emit_bpf_tail_call()
1338 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), lo); in emit_bpf_tail_call()
1344 EMIT3(0x83, add_1reg(0xC0, IA32_ECX), 0x01); in emit_bpf_tail_call()
1349 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0])); in emit_bpf_tail_call()
1397 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_hi)); in emit_push_r64()
1402 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_lo)); in emit_push_r64()
1415 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_lo)); in emit_push_r32()
1572 const u8 arg_regs[] = { IA32_EAX, IA32_EDX, IA32_ECX }; in emit_kfunc_call()
1760 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), in do_jit()
1762 emit_ia32_mul_r(dst_lo, IA32_ECX, dstk, in do_jit()
1780 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), in do_jit()
1783 IA32_ECX, dstk, false, in do_jit()
1803 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), in do_jit()
1806 IA32_ECX, dstk, false, in do_jit()
1825 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32); in do_jit()
1826 emit_ia32_shift_r(BPF_OP(code), dst_lo, IA32_ECX, dstk, in do_jit()
2164 u8 sreg_lo = sstk ? IA32_ECX : src_lo; in do_jit()
2178 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), in do_jit()
2202 u8 sreg_lo = sstk ? IA32_ECX : src_lo; in do_jit()
2215 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), in do_jit()
2235 u8 sreg_lo = sstk ? IA32_ECX : src_lo; in do_jit()
2256 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), in do_jit()
2279 u8 sreg_lo = IA32_ECX; in do_jit()
2335 u8 sreg_lo = IA32_ECX; in do_jit()
2350 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32); in do_jit()
2382 u8 sreg_lo = IA32_ECX; in do_jit()
2396 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32); in do_jit()