Lines Matching refs:REGB_RD32
139 val = REGB_RD32(MTL_BUTTRESS_WP_REQ_PAYLOAD0); in ivpu_pll_cmd_send()
144 val = REGB_RD32(MTL_BUTTRESS_WP_REQ_PAYLOAD1); in ivpu_pll_cmd_send()
149 val = REGB_RD32(MTL_BUTTRESS_WP_REQ_PAYLOAD2); in ivpu_pll_cmd_send()
153 val = REGB_RD32(MTL_BUTTRESS_WP_REQ_CMD); in ivpu_pll_cmd_send()
188 fmin_fuse = REGB_RD32(MTL_BUTTRESS_FMIN_FUSE); in ivpu_pll_init_frequency_ratios()
192 fmax_fuse = REGB_RD32(MTL_BUTTRESS_FMAX_FUSE); in ivpu_pll_init_frequency_ratios()
615 val = REGB_RD32(MTL_BUTTRESS_VPU_D0I3_CONTROL); in ivpu_boot_d0i3_drive()
634 tile_fuse = REGB_RD32(MTL_BUTTRESS_TILE_FUSE); in ivpu_hw_mtl_info_init()
686 val = REGB_RD32(MTL_BUTTRESS_VPU_IP_RESET); in ivpu_hw_mtl_reset()
791 val = REGB_RD32(MTL_BUTTRESS_VPU_STATUS); in ivpu_hw_mtl_is_idle()
852 pll_curr_ratio = REGB_RD32(MTL_BUTTRESS_CURRENT_PLL); in ivpu_hw_mtl_reg_pll_freq_get()
863 return REGB_RD32(MTL_BUTTRESS_VPU_TELEMETRY_OFFSET); in ivpu_hw_mtl_reg_telemetry_offset_get()
868 return REGB_RD32(MTL_BUTTRESS_VPU_TELEMETRY_SIZE); in ivpu_hw_mtl_reg_telemetry_size_get()
873 return REGB_RD32(MTL_BUTTRESS_VPU_TELEMETRY_ENABLE); in ivpu_hw_mtl_reg_telemetry_enable_get()
978 u32 status = REGB_RD32(MTL_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK; in ivpu_hw_mtl_irqb_handler()
988 ivpu_dbg(vdev, IRQ, "FREQ_CHANGE irq: %08x", REGB_RD32(MTL_BUTTRESS_CURRENT_PLL)); in ivpu_hw_mtl_irqb_handler()
997 u32 ufi_log = REGB_RD32(MTL_BUTTRESS_UFI_ERR_LOG); in ivpu_hw_mtl_irqb_handler()
1037 u32 irqb = REGB_RD32(MTL_BUTTRESS_INTERRUPT_STAT) & BUTTRESS_IRQ_MASK; in ivpu_hw_mtl_diagnose_failure()
1055 u32 ufi_log = REGB_RD32(MTL_BUTTRESS_UFI_ERR_LOG); in ivpu_hw_mtl_diagnose_failure()